At first glance, AI competition appears to be a battle of models. Whose model is smarter? Whose reasoning capability is stronger? Whose agent is better at coding, searching for information, and making decisions?

But if we look deeper into the underlying layer, the real factor determining whether AI can continue to scale is hardware. Here, hardware does not simply mean GPUs. It refers to an entire technology chain spanning chips, memory, advanced packaging, networking, power delivery, thermal management, and data center deployment.

In the past, the market liked to use the word “compute” to summarize everything. But by 2026, talking only about compute will become increasingly insufficient. The bottlenecks in AI infrastructure are shifting. Models no longer just require more FLOPS; they also need higher memory bandwidth, lower-latency interconnects, more stable power delivery, and rack-scale systems that can be deployed quickly in real-world data centers.

In 2026, the core question for AI hardware will evolve from “who has the most GPUs?” to:

Who can turn AI compute into commercialized services at lower cost, with higher stability and greater efficiency?

This is why SemiVision believes that what matters in 2026 is not a single company, nor a single chip, but the following seven key keywords.

Together, they represent the transition of AI hardware from the first phase of GPU procurement competition into the second phase of system-level efficiency competition.

Below we will share:

• Inference: The Real Battle Is Only Just Beginning

• HBM: The Scarcest Memory in the AI Era

• CoWoS: Taiwan’s Strategic Position in the AI Supply Chain

• CPO: When AI Clusters Become Too Large for Copper

• Power: Electricity Becomes a Hard Constraint for AI

• ASIC: The Second Path Beyond GPUs

• Rack-Scale System: The Unit of Competition Shifts from Chips to Full Racks

Inference: The Real Battle Is Only Just Beginning

Over the past two years, the market’s attention has been focused primarily on training. Training large models requires massive amounts of GPUs, HBM, power, and advanced packaging capacity. This has benefited NVIDIA, TSMC, SK hynix, CoWoS, and the broader AI server supply chain.

But in 2026, the area more worth tracking is inference.

The reason is simple: training is a capital expenditure for model companies, while inference is the operating cost that AI applications incur every single day. Every chatbot response, every coding agent task, and every enterprise AI workflow consumes inference compute.

Why is inference more complex than training?

Training usually concentrates large amounts of data and compute into a relatively controlled process, with the goal of producing model parameters. Inference is different. It must handle massive numbers of users, requests of varying lengths, different latency requirements, and highly unstable traffic spikes.

Inference can be broadly divided into two stages: prefill and decode.

Prefill sends the user’s prompt into the model and builds the initial state. Decode then generates the answer one token at a time. Prefill is more compute-intensive and relies heavily on matrix operations, while decode is often constrained by memory bandwidth. This is because every generated token requires the system to read model weights and access the KV cache.

This is why long context, agent workflows, and multi-turn conversations can rapidly increase inference cost. When an AI agent needs to read large volumes of documents, query tools, write code, and repeatedly revise its output, it is not simply running the model once. It is turning inference into a long-duration workload with high memory pressure.

In 2026, the core question for AI hardware is no longer simply:

Can the model run?

The real question is:

How much does it cost to process every one million tokens?

This question directly affects the business model of AI. If each agent task requires a large number of tokens, and inference cost cannot be reduced, the gross margin of AI applications will be consumed by hardware cost.

Conversely, whoever can drive down inference cost will have the opportunity to control the next stage of AI commercialization.

Key technical signals to watch in 2026

Read more

The History and Overall Positioning of Japan’s Semiconductor Industry

Japan is an important participant in the global semiconductor industry. After reaching its peak in the 1980s and facing competitive pressure after the 1990s, Japan still maintains extremely strong technological advantages in specialized fields today. In particular, Japanese companies hold world-class market shares in semiconductor manufacturing equipment, materials, testing and inspection, power devices, and automotive electronics.

With the rapid growth of artificial intelligence (AI), the Internet of Things (IoT), autonomous driving, cloud computing, and high-performance computing (HPC), the role of Japanese companies has further deepened. This report classifies these companies into five major functional categories:

1. Strategic Fab Equipment Leaders: including Tokyo Electron, SCREEN Holdings, and Kokusai Electric, which control key technologies in front-end wafer fabrication equipment.

2. AI Test, Inspection & Yield Control: including Advantest, Lasertec, and Tokyo Seimitsu / Accretech, which are responsible for post-fabrication testing and inspection to ensure chip quality and yield.

3. Wafer Materials & Ultra-Precision Processing: SUMCO provides silicon wafers, while DISCO supplies dicing, grinding, and polishing equipment, supporting the foundation of chip manufacturing.

4. Automotive, Power & Specialty Semiconductors: including Renesas Electronics and ROHM, focusing on automotive MCUs, power semiconductors, and silicon carbide (SiC) products.

5. Advanced Packaging & 3DFabric Ecosystem: including IBIDEN, Shinko Electric, Kyocera, Murata Manufacturing, Resonac, TDK, and Taiyo Yuden, focusing on IC package substrates, passive components, packaging materials, and advanced packaging solutions.

Through the above classification, SemiVision will provide a detailed analysis of each company’s technological strengths, product portfolio, market positioning, and its role and future development within the AI industry.

Core Conclusion: Japan May Not Produce the Most AI GPUs, but It Controls Many Critical Links That Make AI Chips Manufacturable

Global discussions around the AI semiconductor industry usually focus on NVIDIA, AMD, Broadcom, Google, Amazon, Microsoft, TSMC, Samsung Electronics, and SK hynix. However, when viewed from the perspectives of manufacturing equipment, silicon wafers, photomask inspection, wafer cleaning, thin-film deposition, grinding and dicing, testing, package substrates, electronic materials, MLCCs, magnetic components, and power semiconductors, the influence of Japanese companies is far greater than the visibility of end-chip brands alone would suggest.

Japan’s core advantages in the AI semiconductor era can be summarized in five areas:

1. It controls equipment and process modules that are difficult to replace in advanced manufacturing.

2. It possesses manufacturing control capabilities related to yield, contamination, dimensional accuracy, defect management, and testing.

3. It controls foundational materials and precision processing technologies, including silicon wafers, packaging materials, grinding and dicing consumables.

4. It provides critical components for AI server power delivery, passive components, and power conversion.

5. It is a major indirect beneficiary of advanced packaging, HBM, chiplets, and high-power AI systems.

Therefore, Japan’s role in AI semiconductors should not be understood simply as whether Japan has an AI GPU company comparable to NVIDIA. Rather, it should be understood as follows:

Japanese companies control many key nodes in AI chip manufacturing that require high precision, high cleanliness, high reliability, high material barriers, and high yield.

As AI chips evolve from single large SoCs toward chiplets, HBM, 2.5D/3D packaging, hybrid bonding, glass-core substrates, high-density substrates, and more complex power delivery networks, the importance of Japanese suppliers will not decline. On the contrary, it may increase as system complexity continues to rise.

Structural Changes Driven by AI Semiconductors

To understand the opportunities for these Japanese companies, we must first understand how AI chips differ from traditional semiconductors.

AI Chips Are Not Simply About “More Transistors”

The growth of AI GPUs, ASICs, and high-performance computing chips is simultaneously driving the following changes:

• Larger logic die area;

• Higher transistor counts;

• More HBM stacks;

• Higher I/O count and speed;

• Larger package size;

• Higher chip power consumption;

• Longer test time;

• Higher defect cost;

• More severe wafer and package warpage;

• Greater challenges in power integrity and thermal management.

As a result, the value of AI semiconductors is no longer concentrated only in chip design and wafer foundry manufacturing. It is spreading across equipment, materials, testing, and packaging.

For example, if a high-end AI accelerator includes:

• One or multiple logic compute dies;

• Eight or more HBM stacks;

• A silicon interposer or RDL interposer;

• A large ABF substrate;

• Tens of thousands of microbumps and C4 bumps;

• A large number of MLCCs, inductors, and power delivery components;

then even a small localized defect could cause the entire high-value package to fail.

This raises the importance of cleaning, inspection, testing, thinning, dicing, packaging materials, and power components.

How AI Changes Yield Economics

For traditional low-cost chips, a defect may result in the loss of only a component worth a few dollars or a few dozen dollars.

But if a large AI package fails during back-end testing, the loss may include:

• Advanced-node logic dies;

• Multiple HBM stacks;

• The interposer;

• The ABF substrate;

• Packaging materials;

• Long equipment capacity time;

• Testing and assembly costs.

Therefore, the more expensive AI chips become, the greater the need for:

• Earlier testing;

• More extensive testing;

• More precise defect inspection;

• Known Good Die;

• More complete wafer sort;

• Stricter process monitoring;

• Better material traceability and statistical process control.

This is exactly where the value of companies such as Advantest, Lasertec, Tokyo Seimitsu (Accretech), SCREEN, Tokyo Electron, and DISCO comes from.

Overview of Japan’s AI Semiconductor Supply Chain

Below, we will share the latest updates and introductions for all the companies listed in the table.

Front-End Process Equipment: Japan’s Most Critical Semiconductor Strategic Asset

Japan holds a significant global market share in wafer fabrication equipment and can provide the etching, deposition, cleaning, bonding, and thermal processing equipment required for front-end manufacturing processes. This section will introduce how companies such as Tokyo Electron, SCREEN, and Kokusai Electric support the demands of AI and advanced process technologies through continuous technological innovation.

Read more

When the market talks about AI servers, the focus usually goes to GPUs, HBM, CoWoS, PCBs, CCLs, optical modules, and liquid cooling. But as AI systems evolve from single servers into rack-scale, and eventually data-center-scale architectures, another long-overlooked component is moving back to the center of the industry’s attention: MLCCs, or multilayer ceramic capacitors.

MLCCs have long been called the “rice of the electronics industry.” The analogy is accurate. Their unit price may seem insignificant, but they exist in almost every electronic system. They handle decoupling, filtering, bypassing, energy storage, voltage stabilization, and noise suppression. They are not as glamorous as GPUs, but they directly determine whether a circuit can operate stably.

According to market report, the global MLCC market was about US$14.8 billion in 2025 and is expected to grow to US$28.6 billion by 2034, representing a CAGR of about 7.6%. Asia-Pacific accounts for roughly 48.6% of the global market, reflecting the core position of Japan, South Korea, mainland China, and Taiwan in MLCC manufacturing and electronics assembly.

But the key point is not merely that the MLCC market is growing steadily. The real change is in demand structure.

In the past, MLCCs were largely viewed as consumer electronics cycle products, moving up and down with smartphones, PCs, and home appliances. Now, they are becoming hard-tech growth components driven by AI servers, electric vehicles, advanced driver assistance systems, 800V high-voltage platforms, and high-speed communications.

This means the investment logic for MLCCs is no longer just about inventory cycles. It now depends on three things: high-end capacity, reliability validation, and access to AI and automotive supply chains.

From the perspective of product type, different MLCCs play different roles.

General-purpose MLCCs mainly provide basic decoupling, filtering, and bypass functions. They are the foundational category used in consumer electronics, home appliances, and general industrial control applications.

High-capacitance MLCCs achieve higher capacitance within a limited package size by increasing the dielectric constant, thinning the dielectric layer, and increasing the number of stacked layers. They are mainly used in applications that are highly sensitive to large-current transient response, such as AI servers and automotive electronics.

Low-inductance MLCCs reduce equivalent series inductance through designs such as reverse terminals and three-terminal structures, maintaining low impedance at high frequencies. They are commonly used in RF front ends and high-speed communication circuits, and are therefore also referred to as low equivalent series inductance, or Low ESL, MLCCs.

Low-ESR MLCCs can reduce losses and heat generation under high ripple current conditions, making them suitable for high-power-density scenarios such as data center power delivery networks.

According to industry report, general-purpose products accounted for 38.4% of the market in 2025, ranking first, mainly supported by the large scale of consumer electronics demand. Their CAGR from 2026 to 2034 is expected to be 6.4%.

High-capacitance products accounted for 24.7%, becoming the second-largest category, with an expected CAGR of 9.1%, higher than that of general-purpose products. This reflects rising demand for high-capacitance and high-reliability MLCCs in AI servers, automotive electronics, and related applications.

Low-inductance and low-ESR products accounted for 14.2% and 15.6% of the market, respectively, with expected CAGRs of 8.8% and 8.5%. Their main application areas include 5G millimeter-wave RF front ends and data center power delivery networks.

Overall, high-capacitance, low-inductance, and low-ESR MLCCs are expected to contribute to market growth at a faster pace.

Below we will share:

• AI Servers Are Pushing MLCCs from the “Thousands” to the “Tens of Thousands” Era

• Compute Board: Semiconductor Integration and the Rise of High-Capacitance MLCCs

• Electric Vehicles Are Moving MLCCs from a “Consumer Product Logic” to a “Reliability Logic”

• Floating design in MLCC

• Where Are the Technical Bottlenecks in MLCCs?

• The Real Question Is Not Whether MLCC Prices Rise — It Is Who Can Capture the High-End Premium

Read more

Introduction: The Vision and Mission of Space Data Centers

In the 21st century, advances in AI models have created unprecedented demand for computing resources. Models centered on training and inference require massive compute power, electricity, and cooling systems. However, traditional terrestrial data centers face constraints in land availability, power supply, and environmental impact, making it increasingly difficult to support long-term expansion.

SpaceX’s concept of “Space Data Centers” aims to leverage its vertically integrated advantages in rocket launches, satellite communications, and AI infrastructure to deploy AI computing nodes in Earth orbit. The objective is to expand compute capacity, reduce energy costs, and ultimately build infrastructure for the Moon and deep space. This concept is rooted not only in the company’s ultimate mission of making humanity a multiplanetary species, but also in response to the current shortage of computing energy.

NVIDIA Launches Space Computing, Rocketing AI Into Orbit

SemiVision provides an in-depth analysis of the background, core technologies, design architecture, operating model, advantages, and challenges of space data centers, while incorporating industry information and SpaceX’s 2026 data and narrative. This article begins with the bottlenecks in terrestrial computing capacity, then explores how SpaceX’s vertical integration and launch capabilities lay the foundation for orbital computing. It then breaks down the composition and operating mechanisms of AI satellites, before finally looking ahead to the future lunar economy, application scenarios, and business models.

Earth’s Computing Demand and Infrastructure Bottlenecks

Surging Global Demand for Computing Power

In the AI era, model scale is growing exponentially. Generative AI, large language models, and scientific computing are rapidly driving demand for compute power. According to roadshow materials, SpaceX had already built and operated the industry’s largest unified supercomputer series, “Colossus,” by 2026, with nominal power consumption reaching the gigawatt (GW) level. The company also deployed a large number of GB200 and GB300 GPUs within a short period of time.

Yet this represents only the tip of the iceberg. As AI models continue to scale, the next generation of training and inference workloads will require even greater computing capacity.

Power Supply and Infrastructure Shortages

The roadshow materials indicate that electricity supply growth in the United States has stagnated, while power generation in China and other regions has continued to rise. In 2025, U.S. supply was only 49 gigawatts (GW), while estimated demand reached 62 GW, revealing a clear supply-demand gap.

The materials also emphasize that both major political parties recognize significant constraints on terrestrial capacity, while 99.8% of Earth’s energy ultimately comes from the Sun. Beyond insufficient power supply, traditional data centers are also constrained by land, cooling requirements, and environmental regulations, creating bottlenecks for large-scale expansion.

The Imbalance Between Computing Demand and Supply

Against this backdrop, terrestrial infrastructure is struggling to keep pace with the explosive growth in AI computing demand. Research from JLL and Introl shows that U.S. electricity supply grew by less than 0.1% between 2008 and 2023, and only around 3% between 2023 and 2025. China, by contrast, recorded growth of approximately 6%.

This means that unless new sources of supply are developed, the gap between compute demand and available infrastructure will continue to widen.

SpaceX’s Vertical Integration and Launch Advantages

An Integrated Platform for Building Future Infrastructure

SpaceX is the only company building an integrated hardware, software, and operations platform across space launch, satellite communications, and AI. The roadshow materials divide its vertical integration into four layers:

• Infrastructure: This includes launch sites, recovery sites, factories, test facilities, and drone ships. In communications, it includes satellite constellations, optical laser networks, ground stations, spectrum licenses, and user terminal production. In AI, it includes turbine power plants, substations, liquid cooling systems, and battery installations.

• Hardware: This covers rockets, engines, reusable boosters, second-stage vehicles, and spacecraft manufacturing. Communications hardware includes user terminals, routers, optical space lasers, and ground antennas. AI computing hardware includes processors, RDMA networks, storage, and fiber optics.

• Software: This includes end-to-end systems for rocket manufacturing and launch, testing, and flight simulation. For satellite platforms, it covers terminal-to-terminal systems, including satellites, ground systems, and dynamic beam allocation, as well as customer-facing application ecosystems. In AI, it includes data from the X platform, dedicated model tools, the Starfleet scheduling system, and compute cluster management.

• Operations: This includes mission control for rocket launches and recoveries, refurbishment operations, constellation management and safety maneuvers, customer support, and AI training and inference deployment.

The seamless integration of these layers enables SpaceX to iterate products rapidly, reduce costs, and horizontally expand its technologies into new markets. The materials emphasize that this “extreme vertical integration” delivers speed and cost efficiency, forming a critical advantage that competitors will find difficult to replicate.

Reusable Rockets and Launch Capability

Since successfully landing a rocket booster vertically for the first time in 2015 and achieving reflight in 2017, SpaceX has continued to drive launch costs sharply lower. According to the roadshow materials, the company has accounted for more than 80% of the total mass launched into orbit globally since 2023.

This dominant position in the launch market lays the foundation for large-scale deployment of Starlink satellites and future AI satellites. Reusability reduces the launch cost per kilogram. Through booster recovery and rapid refurbishment, SpaceX has significantly increased launch frequency, bringing Starship closer to its goal of “airline-like” operations, where the marginal cost of each launch is primarily the cost of fuel.

This makes it possible to launch AI satellites frequently and iterate hardware at a much faster pace.

Starlink Satellite Network

SpaceX has leveraged its launch advantage to build the world’s largest and most advanced low-Earth-orbit broadband network. By the first quarter of 2026, Starlink had more than 9,600 active and maneuverable satellites in orbit, accounting for roughly 75% of all maneuverable satellites worldwide. In 2025 alone, SpaceX deployed more than 3,000 satellites, providing global coverage across 164 countries and regions, with an average daily download speed of 225 Mbps and latency of around 25 milliseconds.

The current V2 satellites are launched 27 at a time, delivering total bandwidth of approximately 2,600 Gbps per launch, or 96 Gbps per satellite. The next-generation V3 satellites, currently under development, are scheduled to begin deployment in the second half of 2026. With Starship, each launch will be able to carry 60 satellites, while per-satellite bandwidth is expected to increase to 1,024 Gbps, representing an overall bandwidth improvement of more than 20 times. Beyond providing high-speed broadband to consumers, the Starlink network also serves enterprises and governments through fixed-site, mobile, maritime, aviation, and dedicated Starshield connectivity services.

4. Starlink Mobile: Direct-to-Cell Satellite Connectivity

Starlink Mobile is the world’s largest satellite-to-cell constellation, using dedicated mobile satellites to complement terrestrial networks and provide coverage across roughly 30 countries. Its first-generation system has around 650 satellites in orbit, delivering 5G-level speeds as well as voice and data services, covering approximately 1.9 billion people. SpaceX plans to begin deploying its second-generation mobile satellites in 2027.

Through partnerships with mobile network operators around the world, Starlink Mobile helps reduce “connectivity dead zones” and provides stable connections for remote regions and maritime operations.

Together, these technical capabilities provide three key foundations for space-based data centers: coverage, power, and data backhaul. Starship enables low-cost launches and large payload capacity; Starlink provides a global, high-bandwidth, low-latency backhaul network; and SpaceX’s vertically integrated manufacturing and software capabilities ensure rapid iteration and lower costs.

Gigawatt-Scale AI Training Clusters and Ground-Based Computing Infrastructure

The Colossus Series Supercomputers

In 2026, SpaceX introduced the Colossus series of AI training clusters, including Colossus I and Colossus II. According to the roadshow materials, the company is the first in the world to build a gigawatt-scale training cluster and deploy large-scale computing based on GB200 and GB300 GPUs. These clusters have a nominal power requirement of up to 1 GW.

Power and Cooling

The Colossus data centers are located in the United States and are equipped with gigawatt-scale battery energy storage systems and advanced liquid-cooling technologies to ensure stable operation of the computing clusters. SpaceX has also pioneered the use of large-scale Megapack batteries combined with renewable energy, making it the first gigawatt-scale Megapack installation. However, the massive electricity demand still remains constrained by local grid supply and power regulations.

Expansion Roadmap

SpaceX plans to expand the next phase of Colossus II by adding more than 400 MW of additional computing power and over 220,000 GB300 GPUs. This would significantly increase the cluster’s capabilities while helping SpaceX accumulate experience for orbital AI computing. However, land-based data centers are constrained by grid supply, land availability, and cooling costs, making unlimited expansion impossible. For this reason, SpaceX has proposed migrating part of its compute capacity into space.

AI Satellites and the Space Data Center Concept

Concept and Origins

The core idea of a space data center is to deploy AI computing payloads—including GPUs, power systems, and thermal management systems—into low-Earth orbit or higher orbits. These systems would be powered by solar energy, cooled through radiative heat dissipation, and connected back to Earth through the Starlink network to return computing results.

This concept is supported by the roadshow materials, which state that orbital AI computing faces “no current regulatory barriers and is environmentally friendly; power comes from solar energy, which is unlimited and cheaper; Starship’s reusable launch capability reduces the cost of access to space; radiative cooling is lower-cost than liquid cooling or air cooling; and the Starlink network enables efficient data flow between orbital clusters and ground users.”

At the same time, next-generation chips can be deployed through frequent launch cycles, greatly improving the efficiency of each hardware refresh cycle.

Structural Design and Modification Strategy

According to the roadshow materials, SpaceX plans to rely on the Starship V3 and Starlink V3 platforms to transform traditional communications satellites into AI satellites. In its design framework, the company proposes three categories of changes: “reduce and remove,” “retain,” and “add.”

• Reduce and remove: Unnecessary backhaul antennas, large-capacity batteries, data modems, and other traditional communications satellite components would be removed to reduce weight and free up space for computing modules.

• Retain: Key attitude-control and communications components would be retained, including ion thrusters, inter-satellite laser communications, flight computers, gyroscopes, reaction wheels, and solar array regulators.

• Add: AI computing modules, larger solar arrays, and radiators would be added to support power generation and thermal management.

A single Starship launch can carry approximately 100 metric tons of payload, while future versions could reach 200 metric tons, making it possible to deploy hundreds or even thousands of AI satellites. In addition, AI satellite design is already underway, and the combination of Starship and Starlink V3 is viewed as a major milestone in removing the technical bottlenecks of orbital computing.

Core Components of AI Satellites — Based on Industry Reports

Analyses from TechNews and other media outlets have visualized the components and specifications of AI satellites, or AI1. The following are the key features, based on information that has not been officially verified and should be treated as reference only:

• Computing module: The core of the AI satellite is a GB300 computing node composed of 72 GPUs, providing efficient AI training and inference capabilities. Similar to Starlink V3 satellites, the computing module adopts a modular design, making it easier to scale.

• Power supply: The satellite uses large solar wings with an output of approximately 250 kW to power the GPUs and auxiliary systems. To ensure continuous power supply during periods without sunlight, the satellite is equipped with a battery pack of around 150 kW and is designed with multi-cycle charge and discharge strategies.

• Thermal management system: Orbital thermal management relies on radiative panels. AI1 uses large radiators and high-efficiency radiative materials to handle the thermal load associated with 1 Tbps data processing demand, with estimated radiative capacity of around 1,400 W/m². The design includes multiple layers of thermal panels connected to form a “thermal chain,” efficiently conducting GPU heat to the radiator surface and dissipating it into deep space.

• Communications and links: AI satellites connect with other satellites and ground stations through inter-satellite lasers and the Starlink mesh network, enabling data backhaul speeds of 1 Tbps. This allows training or inference outputs to be transmitted back to Earth in real time while also receiving new data uploads.

• Size and structure: Media estimates suggest that, after modularization, each AI satellite may measure approximately 3–4 meters in height and 2.5–3.5 meters in width, with a mass of several tons. Starship’s 9-meter-diameter payload bay could carry multiple units in a single launch.

Operating Mechanism and Workflow

The operating workflow of an AI satellite can be summarized as: solar power generation → GPU training/inference → radiative cooling → data backhaul.

1. Solar power generation: Large solar panels collect sunlight and convert it into electricity, eliminating dependence on terrestrial power grids and enabling energy autonomy.

2. GPU training/inference: The GB300 modules inside the satellite run AI models and can execute training and inference tasks for xAI’s Grok models. Since orbital compute nodes can complement ground-based systems, users can allocate workloads based on demand.

3. Radiative cooling: GPU computing generates significant heat. The satellite’s radiative panels dissipate this heat directly into space in the form of infrared radiation, without consuming water or air, thereby reducing ongoing operating costs.

4. Data backhaul: Computing results are transmitted back to Earth through inter-satellite lasers and the Starlink network. Users can obtain results in real time, while data can also be uploaded for the next training cycle. This supports both cloud deployment and edge computing.

Mass Production Plan and Phased Targets

According to media estimates, SpaceX plans to complete the first batch of space-based compute tests before 2027. The target for this phase is to achieve 1 GW of orbital computing capacity, equivalent to the compute power of tens of thousands of GPUs. SpaceX would then expand to 10 GW within 2.5 years and reach 100 GW within 3.5 years. The ultimate long-term goal is to add 1 terawatt, or TW, of equivalent computing capacity per year, roughly twice the electricity consumption of the United States in 2025.

This scale would significantly exceed existing land-based data centers and form the core capability of a true “space data center.”

Differences from Traditional Satellites

The key differences between AI satellites and traditional communications satellites lie in their use cases, structure, and core components:

• Use case: Communications satellites mainly provide broadcasting, communications, or navigation services. AI satellites, by contrast, focus on high-performance computing, AI training, and real-time inference, functioning essentially as “cloud servers in orbit.”

• Simplified structure: AI satellites do not require high-power propulsion systems or complex communications payloads. Their main components are computing modules, radiators, and solar panels, with most of the mass concentrated in GPUs and power systems. By contrast, communications satellites require large antennas, transponders, and propulsion systems.

• Thermal management: AI satellites use large-area radiative panels and thermal chains to dissipate heat into space in a vacuum environment. Communications satellites generate relatively less heat, so their thermal management systems are simpler.

Advantages and Challenges

Advantages

1. Unlimited and low-cost energy: Solar power in space can provide continuous supply without being constrained by terrestrial power grids, while also avoiding carbon emissions.

2. Efficient cooling: A radiative cooling architecture can be lower-cost than liquid or air cooling. The low temperature of deep space also supports more effective heat dissipation.

3. Rapid deployment and upgrades: High-frequency Starship launches could quickly place new satellites into orbit and deploy next-generation chips.

4. Low-latency global coverage: Through the Starlink network, AI satellites can provide millisecond-level latency and deliver cloud and edge services to customers worldwide.

5. Room for cost reduction: With mass production, the unit cost of satellites could decline. Reusable rockets could also push launch costs per kilogram closer to fuel cost.

Challenges

1. Chip manufacturing still depends on Earth: High-end GPUs and advanced chips still need to be manufactured on Earth and cannot currently be produced in orbit. Frequent launches would be required to maintain hardware refresh cycles.

2. Radiation and hardware aging: The orbital environment includes cosmic rays and particle radiation, which may degrade GPUs over time. Radiation-hardened designs or regular satellite replacement would be required.

3. Space debris and collision risk: Increasing orbital density could raise collision risks. Although the Starlink network uses autonomous collision avoidance and propulsion systems, large-scale deployment of computing satellites would require stricter orbital management.

4. Regulation and spectrum: Although the roadshow materials emphasize that there are currently no major regulatory barriers, large-scale satellite use of spectrum and orbital slots would still require international coordination.

5. Recovery and upgrades: AI satellites are large and expensive, and returning them to Earth for recovery would be difficult unless detachable or in-orbit serviceable technologies are developed. Otherwise, they may face one-time depreciation.

Elon: "The AI satellite is much simpler than a Starlink satellite. The AI satellite is essentially a lot of solar cells, you still need some laser links, but you don't have all of the super complex antennas that you have on a Starlink satellite. The easier one to design for is the AI satellite. It's bigger. A lot of this is technology we've already made with the Starlink V3 satellites."

Practical Applications and Business Models

1. Consumer and Enterprise AI Services

SpaceX’s AI business primarily provides “truth-seeking” AI services through xAI’s Grok model. According to the roadshow materials, the latest Grok 4.3 model has reached an advanced level in scientific reasoning benchmarks. Through space data centers, Grok could leverage orbital compute capacity to train larger models, improve inference speed, and reduce user latency. The company has already launched the Grok API and enterprise versions, while also partnering with Cursor to accelerate enterprise adoption.

On the consumer side, SpaceX relies on the X platform, which has approximately 550 million monthly active users and 350 million daily posts. X aims to become an “everything app,” integrating information, social networking, media, payments, and banking services. By deepening subscription and advertising monetization, orbital compute could support real-time content analysis, recommendation systems, and augmented reality features.

2. Compute Leasing and Cloud Services

The roadshow materials indicate that the company has signed cloud computing service agreements to provide Colossus and Colossus II compute capacity to third parties. In the future, AI satellites could extend this model: enterprises could lease orbital compute capacity for AI model training, analytics, or scientific research. Media estimates also suggest that companies such as Google and Anthropic could become customers, paying high monthly fees in exchange for dedicated compute capacity. Orbital compute could compete with terrestrial data centers in terms of power efficiency and performance, offering users faster and lower-cost services.

3. Edge Computing and Low-Latency Applications

Space data centers could provide near-real-time computing services, which would be especially important for applications requiring low latency and wide-area coverage. Examples include:

• Direct-to-cell satellite AI assistants: Starlink Mobile users could send voice commands directly to space data centers, where Grok would process them and return results with latency below 50 milliseconds.

• Aviation and maritime AI: Aircraft cabins and vessels could use AI satellites for route planning, maintenance inspection, and data analysis without relying on ground stations.

• Disaster or battlefield support: When terrestrial infrastructure is damaged or networks are blocked, space-based computing could provide intelligence analysis and communications support.

4. Connection to the Lunar Economy and Deep-Space Exploration

The roadshow’s growth strategy includes “building an economy on the Moon” and “constructing AI satellite factories on the lunar surface.” Starship would transport humans back to the Moon, where local resources and solar energy could be used to build factories that manufacture AI satellites and other equipment. The Moon’s low gravity and lack of atmosphere would reduce launch costs, potentially enabling the use of “mass drivers” to send satellites into orbit.

Over the long term, space data centers could expand from Earth orbit to lunar orbit and beyond, providing computing support for Mars colonization and interstellar travel.

5. Supporting the Advertising and Media Ecosystem

The X platform uses AI recommendation and media generation to help advertisers achieve more precise targeting. The roadshow materials mention that the company has launched X Ads Manager and is gradually improving its advertising capabilities. Through space data centers, X could provide low-latency content generation and analytics services worldwide, improving user experience and increasing advertising revenue.

Meanwhile, the Imagine image-generation feature produces billions of images and videos each month, which could be rendered in real time using orbital compute capacity.

6. Government and Military Applications

The Starshield program provides secure networking and computing services for governments. Space data centers could be used for military intelligence analysis, satellite imagery processing, and encrypted communications, offering defense agencies a faster-response and more secure cloud platform. In addition, international partners could access compute capacity by leasing computing satellites, supporting cross-border scientific research and security cooperation.

Analysis of Technical and Economic Challenges

1. Large-Scale Production and Launch

Although SpaceX has reusable rockets and rapid launch capabilities, deploying tens of thousands of AI satellites within just a few years would still require enormous manufacturing capacity and supply chain support. Satellite production would require precision GPUs, batteries, and radiators, all of which must also meet radiation-tolerance standards. Any supply chain bottleneck could affect the entire plan. On the launch side, Starship would need to operate reliably and secure regulatory approvals, as it is still in the testing phase.

2. Orbital Congestion and Regulation

As Starlink, other private satellite operators, and national satellite constellations continue to expand rapidly, congestion in low-Earth orbit is becoming an increasingly serious issue. SpaceX would need to coordinate with regulators across multiple countries on orbital allocation, collision-avoidance standards, and spectrum resource distribution. Although SpaceX uses automated collision-avoidance systems, the large-scale deployment of AI satellites would still require global coordination.

3. Radiation Protection and Thermal Management

Cosmic rays can affect electronic components, especially GPUs. Radiation-hardened chips or additional shielding would be required to protect the circuitry. At the same time, radiators would be exposed over long periods to both sunlight and extremely cold environments, so material aging and thermal stress must be considered. Balancing thermal efficiency and weight would be one of the key design challenges for AI satellites.

4. System Maintenance and Lifespan

After operating for several years, AI satellites may fail due to hardware aging or orbital decay. In-orbit servicing technologies are not yet widely available. In the future, robotic servicing, detachable modules, or automated de-orbiting and disposal could be considered to reduce space debris. SpaceX may adopt a high-speed iteration model, replacing older satellites with newly launched ones. This would require well-managed recovery and retirement procedures.

5. Economics and Payback Period

The upfront investment required to build and launch AI satellites would be extremely high. Although reusable rockets reduce transportation costs, the cost of each satellite—including GPUs, batteries, and radiators—would still be substantial. The business model must ensure that leasing and service revenue can recover the investment within a reasonable timeframe while continuing to support future upgrades and expansion.

In addition, price-sensitive customers may still prefer terrestrial cloud services. Therefore, clearly demonstrating the advantages of space data centers and setting a rational pricing strategy will be a key challenge.

6. Advanced Packaging

SpaceX’s FOPLP technology has been confirmed to come from PEP’s advanced packaging platform, particularly its panel-level packaging capabilities and key technologies developed for high-reliability interconnects. PEP’s technology covers core capabilities such as electromigration reliability, fine-line redistribution layers, high-density interconnects, and heterogeneous integration, all of which are essential foundations for the continued scaling of AI, high-performance computing, and large-format packaging.

Why SpaceX is Using FOPLP

• Cost & Scale: FOPLP reduces the edge waste associated with traditional wafers, allowing SpaceX to mass-produce critical components (like satellite RF chips and power management ICs) much faster.

• U.S. Manufacturing: By pushing for domestic and localized packaging lines, Elon Musk is aiming to decouple SpaceX’s production lines from Asian-dominated foundries to meet strict U.S. national security and government contracts.

  

Current Industry Status

• In-House Fab Plans: SpaceX is currently establishing massive, 700mm x 700mm FOPLP lines at a multi-billion dollar facility in Texas, which will be one of the largest substrate dimensions in the industry.

• Production Timeline: While facilities are being built, setting up the new FOPLP infrastructure is facing yield rate and talent constraints, with the major in-house scaling operations slated to mature between 2026 and 2027.

Future Outlook

• Major Opportunities on the Moon and Mars

  SpaceX’s long-term goal is to build a lunar economy and establish a Mars colony. According to the roadshow materials, SpaceX aims to use Starship to bring humans back to the Moon by the end of the 2020s, establish lunar bases, and manufacture AI satellites there. The Moon has abundant solar energy resources and lower gravity, making it suitable for manufacturing and launching large satellites. In the future, SpaceX could even develop energy production and manufacturing capabilities on Mars, leverage asteroid mining, and build an interplanetary network, ultimately forming a multi-planet space data center system.

• Expansion into New Markets

  Once space data centers scale up, they could provide highly competitive computing solutions for artificial intelligence, scientific research, financial services, high-frequency trading, global communications, and entertainment. SpaceX’s business model would span three major domains: launch services, satellite internet, and AI platforms. By integrating digital advertising, subscriptions, and compute leasing revenue, the company could build a moat that is difficult to replicate.

• 3. Technological Evolution and Social Impact

  Over the long term, space data centers could fundamentally change how humanity uses resources and computing. By combining solar energy, vacuum-based thermal dissipation, and global communications, they could form a borderless and continuously expanding computing platform. This would not only advance AI research, but also enable new industrial models such as in-orbit manufacturing, space-based healthcare, and navigation for interplanetary travel.

  At the same time, their environmental, regulatory, and ethical implications must be carefully assessed to ensure the sustainable use of space.

Conclusion

SpaceX’s space data center plan represents a major leap forward in both computing and space exploration. It is not a single product, but an integrated system combining reusable rockets, a global satellite network, AI models, and orbital manufacturing. Through vertical integration and a “first-principles thinking” engineering philosophy, SpaceX continues to simplify requirements, remove unnecessary processes, optimize designs, accelerate iteration, and implement automation—allowing it to achieve engineering milestones that would be unimaginable to most.

Against the backdrop of global power shortages and surging demand for compute capacity, space data centers offer a forward-looking solution. They convert solar energy into computing power and bring resources beyond Earth into the human economic system.

Although technical and economic challenges remain, this vision opens up vast possibilities for technological and economic development over the coming decades. As Starship, Starlink, and AI platforms continue to mature, space data centers may move from concept to reality, leading a compute revolution in the multi-planet era.

Remark…

On June 29, 2010, Elon Musk, CEO of Tesla Motors, waved after ringing the opening bell at the NASDAQ Market in New York to celebrate Tesla’s initial public offering. Looking back, that moment was more than just the listing of an electric vehicle company—it marked the beginning of a new industrial era. Elon Musk is a truly great entrepreneur. His courage, persistence, and first-principles thinking are worth learning from.

One of my favorite ideas from him is simple but powerful: no one can stop you except the limits of your own imagination.

OPTICKS VISION *_*

When Others Use AI to Cut Jobs, Jensen Huang Uses AI to Expand the Future

The AI era has created a strange paradox…

Read more

3 months ago · 5 likes · SEMIVISION

Computex 2026, held in Taipei in June 2026, featured a GTC Taipei keynote personally hosted by NVIDIA CEO Jensen Huang, putting Taiwan’s supply chain on the global AI stage. At the opening, Huang emphasized the feeling of “coming home” and thanked Taiwan’s vast ecosystem of partners. This two-hour keynote not only drew global attention to the full-scale development of AI across data centers, consumer electronics, and the physical world, but also provided an in-depth analysis of the Agentic AI era.

During the keynote, NVIDIA announced several major products and platforms, including the DSX AI Factory, the Vera Rubin platform, Vera CPU, RTX Spark AI PC, Nemotron 3 Ultra model, Cosmos 3 Physical AI model, and Isaac GR00T robotics platform. NVIDIA also emphasized that Taiwan is at the heart of the AI revolution, with a supply chain spanning 150 Taiwanese partners, more than 350 factories, and 30 countries.

Below Paywall, we provide the latest updates on selected Taiwanese companies.

Core Themes of GTC Taipei 2026

1. Agentic AI: AI Has Moved from Generation to Execution

During the GTC Taipei keynote, NVIDIA CEO Jensen Huang declared that AI has entered the Agentic era. He pointed out that a standalone large language model can only answer questions, while an agent combines models with a safety framework, or Harness, allowing AI to understand tasks, observe environments, reason, and use tools to complete work. NVIDIA’s Agent Toolkit provides models, runtime, and tool layers to help enterprises build trustworthy agents on their own workloads.

The essence of Agentic AI is a fundamental shift in the computing model. Traditional computing is application-centric: users open an app and enter commands. In the future, users will simply describe their intent, and agents will automatically generate code, call tools, and complete tasks. This intent-to-code model will cause compute, memory, tools, and network resources to switch frequently, requiring data centers to be redesigned at the system level, from chips and racks to power, cooling, and networking.

Huang noted that over the past three years, people have continued to question the practical value of AI, while generative AI has already proven itself in content creation and natural language processing. He further emphasized that Agentic AI is the next computing model: agent = LLM + Harness. A standalone large language model is merely a brain that can chat. To allow AI to truly work for humans, it must be paired with a framework capable of calling tools, managing memory, and executing plans.

This two-layer architecture includes a reasoning/planning model at the bottom and an orchestration engine on top. Users only need to express their needs through voice or text, and AI agents can automatically call software tools to complete tasks.

2. DSX AI Factory: From Data Center to AI Factory

NVIDIA introduced the concept of the DSX AI Factory, arguing that modern data centers are transforming into AI factories that generate intelligence. These factories integrate five layers: energy, chips, networking, software models, and applications. DSX includes the DSXSim design and validation platform and the DSXOS operating system. Before an AI factory is built, Omniverse can be used to simulate facility layout, power, cooling, and network topology. During actual operation, DSXOS is responsible for allocation, monitoring, and remediation, turning the AI factory into an operable computing asset.

The economic significance of the AI factory lies in the concept of “compute per watt as revenue.” As agentic workloads rise sharply, token output becomes a source of enterprise revenue. Investors are no longer comparing the price of a single GPU, but rather how many tokens and how much inference throughput can be generated under a fixed power budget. Therefore, the efficiency of power, cooling, networking, and memory will directly determine the return on investment of AI factories.

DSX is NVIDIA’s end-to-end AI factory solution. It integrates energy, chips, networking, software models, and applications into a five-layer architecture, with the goal of building and operating AI factories at the lowest token cost per watt.

The platform provides tools such as DSX OS, Omniverse digital twins, and DSX Sim. These tools can simulate power, cooling, and network layouts before data centers are built, and monitor resource allocation and dynamic power distribution after deployment. This “build it right the first time” capability can significantly reduce the trial-and-error cost of massive AI factories, where each gigawatt-scale facility may require an investment of US$8 billion to US$10 billion.

3. Vera Rubin Platform and Vera CPU

Vera Rubin is NVIDIA’s next-generation pod-level supercomputer designed for Agentic AI. It consists of five racks and combines the Vera Rubin GPU, Vera CPU, Groq 3 LPU, BlueField-4 STX storage, and Spectrum 6 SPX Ethernet systems into a fully integrated platform.

The Vera Rubin system features 18 compute trays, 9 hot-swappable NVLink switch trays, high-efficiency liquid-cooling manifolds, and busbars. A single MGX rack contains approximately 1.3 million components.

Vera CPU is a new processor designed specifically for Agentic AI. It features 88 cores, 1.2 TB/s of LPDDR5X memory bandwidth, and an on-chip interconnect fabric reaching 3.6 TB/s. Huang emphasized that the future role of the CPU in AI factories will shift from a simple compute core to a “conductor” that coordinates GPUs, manages memory, and handles tool invocation, supporting agent planning and reasoning with extremely low latency.

Full production of Vera Rubin has already begun. Assembly time has been reduced from two hours in the previous generation to five minutes, demonstrating the importance of modular design in improving manufacturing efficiency and reliability.

Vera Rubin: An AI Factory Built for Agentic AI

Vera Rubin is NVIDIA’s largest pod-level platform to date. It is a massive supercomputer composed of five dedicated racks, including the Vera Rubin NVL72 system, Vera CPU, Groq 3 LPX low-latency processor, Vera BlueField 4 STX storage security system, and Spectrum 6 SPX Ethernet rack.

Each rack adopts a cableless, pipeless, and fanless design. Through the use of PCB midplanes, assembly time per rack has been reduced from two hours to five minutes. Compared with the previous Grace Blackwell generation, Vera Rubin delivers a 10x improvement in agent throughput.

Supply Chain Scale and Partners

The success of Vera Rubin depends on a vast supply chain. NVIDIA stated that the supply chain built for Vera Rubin is twice the scale of Grace Blackwell, involving 150 Taiwanese partners across more than 350 factories in 30 countries.

Major system and storage partners include Dell Technologies, HPE, Lenovo, Supermicro, AIC, ASRock Rack, ASUS, Compal, Foxconn, GIGABYTE, Inventec, MiTAC Computing, MSI, Pegatron, Quanta Cloud Technology, Wistron, Wiwynn, and others.

In addition, Quanta Computer founder Barry Lam, TSMC CEO C.C. Wei, and other Taiwanese industry leaders met with Jensen Huang during GTC, highlighting NVIDIA’s deep connection with Taiwan’s manufacturing ecosystem.

Vera CPU: A Processor Built for Agents

Vera CPU is built on the Olympus Core architecture, emphasizing single-thread performance, high bandwidth, and energy efficiency. Its 88 cores provide 1.2 TB/s of LPDDR5X memory bandwidth and a 3.6 TB/s on-chip fabric. The single-die design avoids the latency introduced by traditional chiplet architectures.

NVIDIA emphasized that the number of future agents will far exceed the number of humans. Therefore, CPUs must reduce latency to avoid slowing down expensive GPUs’ token-generation efficiency. For this reason, Vera CPU prioritizes single-core performance and available bandwidth per core, rather than simply increasing core count.

In enterprise application testing, Vera CPU is approximately three times faster than traditional x86 CPUs in SQL workloads, and improves real-time data stream processing speed at the New York Stock Exchange by roughly six times. This demonstrates its advantage in database queries and real-time data analytics.

4. RTX Spark: Redefining the Personal Computer

Beyond data centers, NVIDIA also partnered with MediaTek to launch the RTX Spark chip. This personal AI PC platform features a 20-core CPU, 6,144 CUDA cores, and 200 TOPS of local AI compute. The first wave of products is expected to launch in fall 2026, offering ultra-thin 14- to 16-inch laptops with a thickness of around 14 mm.

The core significance of RTX Spark is that it enables PCs to securely run local agents. Agents can use tools locally, connect to cloud or on-premises models, and rely on sandbox mechanisms to prevent data leakage. This not only creates demand for high-performance CPUs/GPUs, cooling, and memory among Taiwan’s notebook ODMs, but also pushes AI PCs beyond the NPU performance race toward CUDA ecosystems and local agent platforms, expanding the value-add of the PC supply chain.

Hardware Characteristics

RTX Spark is an AI PC platform jointly developed by NVIDIA and MediaTek. It uses TSMC’s 3nm process and integrates a Blackwell RTX GPU with 6,144 CUDA cores and FP4 Tensor Cores capable of up to 1 PFLOPS of AI performance, along with a 20-core Grace CPU. It connects through NVLink C2C and supports 128 GB of unified memory.

The platform supports Windows and is fully compatible with CUDA. Its design goal is to create an always-on device built specifically for personal agents.

The New Role of the PC

RTX Spark signals that the future PC will no longer be just a device for running applications. It will become a “home AI server” that runs AI agents, manages personal data, and coordinates tools.

NVIDIA predicts that every person will have multiple AI agents, and every household will need an always-on AI PC. As a result, the PC market will no longer be limited by the number of people, but will expand with the number of agents.

This also means that PCs will become part of NVIDIA’s product roadmap. In the future, every generation of data center GPU architecture will have corresponding versions for desktops, notebooks, and workstations.

5. Enterprise AI Toolkit and Enterprise Agents

NVIDIA introduced a complete Enterprise AI Toolkit that enables companies to build their own agent operating systems. The major components include:

Model layer: The Nemotron 3 Ultra model adopts a Mixture-of-Experts architecture and is trained for long-horizon reasoning and tool-calling tasks. It delivers inference speeds five times faster than competing models and reduces cost by 30%.

Harness layer: Agent Harness, such as OpenShell, is responsible for workflow orchestration and security management. It provides sandboxing, permissions, and security policies to ensure that agents can operate safely inside enterprises.

Tools/Skills layer: CUDA X Libraries, Cadence EDA tools, enterprise software, and other resources are made available as tools for agents to call. Through Skills, agents are taught how to use these tools. NVIDIA noted that agents will become the most important users of tools, and the value of software companies will rise as agents use their tools more frequently.

Runtime layer: OpenShell provides a secure execution environment that can run in the cloud, on enterprise servers, or on devices.

Through these components, enterprises can build Super Agents based on their own knowledge. For example, NVIDIA’s collaboration with Cadence on a Chip Design Super Agent automates RTL generation, testbench creation, regression testing, and debugging. Processes that previously took weeks can now be shortened to hours, improving efficiency by more than 40 times.

6. Physical AI and Cosmos 3

Agentic AI is also extending into the physical world. At GTC, NVIDIA introduced Cosmos 3, an Omnimodel capable of reasoning, world simulation, and action generation using multimodal data such as vision, motion, and language.

The model comes with an open-source toolkit that simplifies data generation and simulation workflows, helping developers build robots and autonomous systems that can understand, reason about, and simulate the physical world.

The biggest bottleneck for Physical AI is the lack of first-person operational data. NVIDIA addresses this through teleoperation, simulation, and world models that generate physically consistent synthetic data, turning compute into data.

Cosmos 3 uses a hybrid Transformer architecture to process images, actions, audio, and text, generating worlds that conform to physical constraints. NVIDIA also introduced the Isaac GR00T humanoid robotics platform and the Alpamayo autonomous driving reasoning model, extending Agentic AI into robotics and self-driving vehicles.

Physical AI: From Virtual to Physical

Cosmos 3 Omnimodel

NVIDIA introduced Cosmos 3, an Omnimodel that learns from teleoperation, simulation, and third-person video to understand the world. The model has visual reasoning, world simulation, and action-generation capabilities, making it suitable for robotics and autonomous systems.

Cosmos 3 includes an open-source toolkit that simplifies data generation, simulation, training, and validation workflows, helping developers build robots that can understand and simulate the physical world.

Isaac GR00T Robotics Platform

Isaac GR00T is a humanoid robotics development platform that integrates the Jetson Thor computing platform, Isaac Lab simulation environment, Isaac Teleop demonstration learning, Omniverse simulation system, Cosmos World Model, Isaac ROS Runtime, and more.

Together, these components form a complete closed loop from data generation and model training to deployment. The platform also provides reference designs, allowing research institutions and enterprises to begin robotics development without having to build the underlying system from scratch.

Alpamayo 2 Autonomous Driving Platform

In autonomous driving, NVIDIA introduced the Alpamayo 2 open model and the Hyperion vehicle platform. Alpamayo 2 integrates perception, understanding, reasoning, and planning into a single model. Hyperion provides compute resources and sensor integration, while the Halos Operating System handles task scheduling and vehicle control.

Together, these three components form a complete autonomous driving architecture.

Taiwan’s Supply Chain and Industrial Opportunities

Taiwan’s Role in the Global AI Supply Chain

Taiwan is a critical hub in the global AI supply chain. Reuters has noted that Taiwan plays a pivotal role in the global AI supply chains of companies including NVIDIA and Apple, with its position reinforced by companies such as TSMC. NVIDIA plans to invest approximately US$15 billion per year in Taiwan and build a new headquarters in the Beitou-Shilin Technology Park, designed to accommodate 4,000 employees and expected to begin operations in 2030. Jensen Huang has described Taiwan as the “epicentre” of the AI revolution, and this move will further strengthen NVIDIA’s collaboration with manufacturing partners such as TSMC, Quanta, and Foxconn.

Beneficiaries Across the Supply Chain

1. Semiconductor Manufacturing and Packaging & Testing
   Vera Rubin, Vera CPU, and RTX Spark are all manufactured by TSMC using N3 and CoWoS technologies. Testing and packaging are supported by Taiwanese companies such as KYEC and Powertech Technology. The Vera rack design reduces copper wire usage and shortens assembly time, highlighting Taiwan’s advantages in hardware manufacturing and modular system assembly.

2. Memory and Storage
   Agentic AI requires extremely high bandwidth, driving strong demand for LPDDR5X and HBM4. Original manufacturers such as Micron, Kioxia, and SanDisk are expected to benefit, while Taiwan’s NAND module supplier Phison and packaging and testing company Powertech Technology may also see opportunities. The high-speed networking and storage processing required by Vera BlueField 4 STX and Spectrum 6 SPX could further benefit memory suppliers such as Nanya Technology and Elite Semiconductor Microelectronics Technology.

3. BMC / IPMI Controllers
   AI racks require BMC management and remote monitoring. Taiwan’s ASPEED is the world’s largest supplier of BMC controllers, and its product penetration is expected to rise alongside growing demand for AI server racks.

4. Thermal Management and Power
   Vera Rubin and LPU racks adopt liquid-cooling designs, increasing the penetration of both liquid-cooling and air-cooling thermal solutions. Taiwanese thermal solution providers such as Auras, Fujikura, and Jentech have strong competitiveness in cold plates, cold heads, and thermal modules. Power supply companies such as FSP Group and Delta Electronics are also positioned to benefit from rising demand for high-power racks.

5. Server and PC Assembly
   The launch of RTX Spark repositions the PC as a home AI server in the era of agentic AI. Taiwanese PC and notebook makers such as ASUS, MSI, ASRock, Quanta, Compal, Pegatron, and GIGABYTE are expected to launch laptops and desktops equipped with RTX Spark. Major server ODMs including Foxconn, Inventec, Quanta QCT, Wistron, and Wiwynn have already partnered with NVIDIA to produce Vera Rubin systems and MGX servers.

6. Networking and Communications
   The Spectrum 6 SPX Ethernet rack adopts 200G CPO technology, creating potential opportunities for Taiwanese optical communication suppliers such as Coretronic, Lextar, and Lite-On. The storage acceleration functions of BlueField 4 STX require high-speed chips and FPGA-related solutions, areas where Taiwanese companies such as Accton and MiTAC may provide relevant support.

Driven by the rise of agentic AI and the concept of AI factories, Taiwan’s supply chain showcased a complete ecosystem at Computex 2026, covering chip manufacturing, advanced packaging, system assembly, racks, thermal management, power infrastructure, and end applications.

Below, we provide the latest updates on selected Taiwanese companies at COMPUTEX 2026

Read more

Why Korea Is Not Just a Supporting Player in the AI Supply Chain, but a Key Battleground for the Next Wave of AI Industrialization

After leaving Taiwan, Jensen Huang traveled to South Korea, and the country quickly witnessed a familiar scene: media outlets chasing his motorcade, crowds gathering around him, corporate leaders lining up for meetings, financial communities tracking his itinerary in real time, and even investors mapping each stop on his trip to related Korean stocks as an “AI wealth map.”

This was no ordinary visit by a corporate CEO. It looked more like a technology version of a K-pop superstar tour.

But if we simply interpret this as “Jensen Huang is popular,” we miss the deeper point. The real question is: Why is South Korean society paying such close attention to NVIDIA? Why would his meal of grilled pork belly, his meeting with Faker at a PC café, his appearance on a variety show, and his ceremonial first pitch at a baseball stadium all be interpreted as part of Korea’s industrial destiny?

The answer is simple: in the AI era, South Korea occupies an extremely critical position.

Korea is not the world’s largest semiconductor foundry base, nor is it the main assembly hub for AI servers. But it controls several indispensable nodes in AI infrastructure: HBM memory, advanced-packaging-related capabilities, semiconductor materials and equipment, consumer electronics brands, automobile manufacturing, robotics, internet platforms, and sovereign AI demand.

In other words, Korea is not merely a single-component supplier. It is a national-level platform capable of bringing AI from data centers into factories, vehicles, robots, and consumer applications.

That is why Jensen Huang’s popularity in Korea is not merely personal admiration. Behind it lies industrial anxiety, national expectation, and a concentrated desire to secure a ticket into the AI era.

Korea Is Not Chasing Jensen Huang. It Is Chasing a Ticket Into the AI Era

One of the most symbolic moments of Jensen Huang’s visit to Korea took place at a grilled pork belly restaurant, one of South Korea’s most beloved national food venues. There, he met with three major Korean business leaders: SK Group Chairman Chey Tae-won, LG Group Chairman Koo Kwang-mo, and Naver Chairman Lee Hae-jin. The gathering was described by some as a “Korean version of a trillion-dollar dinner.”

The scene itself was highly symbolic.

Around the sizzling barbecue table sat some of Korea’s most powerful technology and conglomerate leaders. Among them, LG Group Chairman Koo Kwang-mo, the youngest of the group, was even seen somewhat awkwardly grilling meat for everyone. This was a scene ordinary Koreans had rarely imagined, let alone witnessed.

Korea’s chaebol culture has long carried a sense of distance, hierarchy, and mystery. Yet Jensen Huang’s presence pulled these top-tier business leaders onto the same barbecue table, turning them into a surprisingly down-to-earth and human scene.

Even more interestingly, Huang walked outside the restaurant to greet the crowd and hand out food and drinks. The atmosphere felt less like a closed-door meeting among global technology giants and more like a K-pop idol fan meeting.

This is precisely what makes Jensen Huang so effective.

He understands that AI is no longer just a technical issue. It is a combination of social narrative, national competition, industrial confidence, and public emotion. That is why he did not merely meet corporate leaders. He met Korean society itself.

Jensen Huang Knows How to Play the Culture Card: From Faker and Yoo Jae-suk to a KBO First Pitch

Jensen Huang’s team clearly understands that Korea is not a market that can be won over only inside boardrooms. Korea has its own mass culture, esports culture, variety-show culture, baseball culture, and food culture.

That is why this visit was not just a series of corporate meetings. It was a carefully designed exercise in cultural communication.

He visited a PC café, met legendary esports player Faker, and posed with him using a signature hand gesture. This mattered deeply to Korea’s younger generation, because Korean PC gaming and esports culture were part of the early growth environment for NVIDIA’s GPUs.

South Korea was one of the earliest countries to turn gaming into a mainstream culture. From the rise of PC bangs in the late 1990s to the professionalization of StarCraft and League of Legends, esports became part of Korea’s national technology identity. Teams like T1 and players like Faker are not just entertainers; they represent Korea’s ability to build global digital culture, talent systems, fan economies, and competitive platforms.

For NVIDIA, this history matters. Korea’s relationship with GPUs did not start with AI data centers. It started with gaming, graphics cards, PC cafés, and esports. By standing beside Faker, Huang was reminding Korea that the AI era is not disconnected from its gaming past. The same GPU ecosystem that powered Korean esports is now powering the next generation of AI infrastructure.

NVIDIA’s relationship with Korea is not just about HBM, nor did it begin with today’s AI cooperation. From gaming graphics cards and PC cafés to esports, AI data centers, and robotics, NVIDIA and Korea’s technology industry have grown together over time.

Huang also made his first appearance on a South Korean variety show, joining Yoo Jae-suk on the popular program You Quiz on the Block. He even danced to “Golden,” the theme song from the animated film KPop Demon Hunters.

These moments looked lighthearted, but they were actually highly precise public-relations moves.

Bloomberg has described Huang as a natural showman. Through these events, he fully displayed an image closer to that of a rock star than a traditional technology executive.

This approachable, hierarchy-breaking style created a major sensation in Korea.

Korean society has long had a complicated relationship with chaebols, power, and technology elites: admiration mixed with distance, dependence mixed with suspicion. Huang used restaurants, PC cafés, variety shows, and baseball stadiums—highly public, everyday spaces—to repackage the otherwise cold and distant image of the AI industry.

AI was no longer just an invisible GPU inside a data center, nor merely a capex number in a Wall Street report. It became a wave of change that ordinary people could feel.

The KBO First Pitch: The Industrial Signal Behind One Jersey Number

Another highlight of Huang’s Korea visit was his appearance at Jamsil Baseball Stadium in Seoul, where he threw the ceremonial first pitch before a KBO game between the Doosan Bears and the Kiwoom Heroes.

Known for his signature black leather jacket, Huang changed into a baseball look this time, wearing a jersey with the number “93.” This number was not chosen at random. It paid tribute to 1993, the year NVIDIA was founded.

Standing in the batter’s box to “face” Huang’s pitch was Doosan Bears owner and Doosan Group Chairman Park Jeong-won. Park wore the number “96,” symbolizing Doosan Group’s founding year of 1896.

On the surface, this was a lighthearted baseball event. But beneath it was a powerful industrial symbol.

NVIDIA represents a new technological force born in 1993, while Doosan represents Korea’s traditional industrial power dating back to 1896. When an AI giant and a century-old industrial group appeared together on a baseball field, the message was clear: AI is not here to replace traditional industry. It is here to reshape it.

This matters especially for Korea.

Korea’s next AI opportunity is not only about data centers and HBM. It is also about how AI enters heavy industry, robotics, energy, manufacturing, and automation systems. Doosan itself is closely tied to robotics, energy equipment, and industrial manufacturing, which aligns strongly with NVIDIA’s push into robotics and physical AI.

Before throwing the pitch, Huang also said that NVIDIA’s relationship with Korea began with PC gaming. He said that NVIDIA and Korea’s PC gaming industry, as well as NVIDIA and Korea’s technology industry, grew up together.

That statement matters.

It was not just a polite remark. It was a reminder to Korea that NVIDIA is not an AI giant that suddenly arrived in the country. Since the gaming GPU era, NVIDIA and Korea’s technology industry have shared a common history.

From PC gaming to AI computing; from PC cafés to AI factories; from gaming GPUs to HBM and robotics. This trajectory is also a miniature version of Korea’s own technology transformation.

Chimaek Diplomacy: Supply Chain Politics Behind Fried Chicken and Beer

Huang also joked that another important reason for visiting Korea was to enjoy “chimaek,” Korea’s beloved pairing of fried chicken and beer.

He even said, “Nothing is better than chimaek.”

It sounded casual, but the impact was powerful.

To Koreans, chimaek is not just food. It is a cultural symbol of everyday life. By placing himself inside this familiar Korean cultural language, Huang quickly shortened the distance between himself and the public.

Even more notably, after saying he wanted to enjoy fried chicken and beer, his next stop was a nearby fried chicken restaurant for a “chimaek” gathering with SK Group Chairman Chey Tae-won.

This was no longer just a food stop. It was culturally packaged supply chain diplomacy.

The AI-era supply chain is extremely complex. If any node fails, the entire platform’s shipment schedule can be affected. Without enough HBM, GPUs cannot ship. Without enough CoWoS, AI accelerators cannot be packaged. If PCB lead times stretch, racks cannot be delivered. If liquid cooling is immature, data centers cannot operate stably. If power is insufficient, no amount of GPUs can be turned on.

Therefore, NVIDIA does not merely need suppliers. It needs allies.

Through grilled pork belly, chimaek, baseball, esports, and variety shows, Huang transformed supply chain relationships from cold procurement contracts into public recognition, national pride, and corporate community.

When he appeared in public cultural settings with leaders from SK, LG, Naver, Doosan, and other Korean companies, the message was not “we held a meeting.” The message was: “Korea is an important member of NVIDIA’s AI map.”

That signal is extremely effective for companies, governments, investors, and the general public.

Why Korea Matters: Its First Trump Card Is HBM

The bottleneck in AI training and inference is no longer just GPU compute power. It is data movement. The larger the model, the greater the parameter count, and the higher the token throughput, the more GPUs depend on high-bandwidth, low-latency, low-power memory systems.

That is why HBM has evolved from a relatively niche high-end memory product into a strategic component for AI accelerators.

This is where Korea matters.

SK hynix is one of the most important suppliers in the global HBM market, while Samsung is aggressively catching up, hoping to regain its influence in high-end memory. For Korea, whether NVIDIA’s next-generation platforms adopt Korean HBM is not just a routine supply chain story. It is a central question that will shape memory capex, pricing cycles, and national technology status for years to come.

As AI chip architectures evolve, HBM increasingly looks less like conventional “memory” and more like a co-designed component inside the GPU package.

By the Rubin, Rubin Ultra, and later platform generations, HBM is no longer a commodity that can simply be plugged in. It involves base dies, TSVs, thermal management, package height, yield, power consumption, signal integrity, and total system cost.

Whoever can supply stable, sufficient, and qualified HBM can become deeply tied to the next-generation architectures of NVIDIA, AMD, Google, Amazon, Microsoft, Meta, and other AI platform companies.

This is why Korean investors are chasing Jensen Huang.

One sentence from him may determine not only the short-term stock price of a company, but also whether Korea’s memory industry can remain at the core of AI for the next several years.

Korea’s Value Is Not Only Memory, but Industrialization Capability

If we look only at HBM, Korea is already important. But if we look at AI deployment, Korea becomes even more important.

During his Korea visit, Huang specifically said robotics will become Korea’s next major industry. This was not accidental.

Korea is already a global manufacturing powerhouse. It has automobiles, home appliances, semiconductors, displays, batteries, industrial machinery, shipbuilding, logistics, and smart factories. These are precisely the best scenarios for AI to enter the physical world.

Hyundai Motor represents mobility and robotics. LG represents home appliances, displays, batteries, and smart factories. Samsung represents semiconductors, smartphones, terminals, and AI devices. SK represents memory, energy, and telecommunications. Naver represents cloud, search, content, language models, and sovereign AI.

These companies are not isolated corporations. They are part of Korea’s industrial system.

Therefore, what NVIDIA wants to do in Korea is not merely to buy HBM. It is more likely looking for the next wave of major collaboration cases in AI factories, robotics platforms, smart manufacturing, sovereign AI, and physical AI.

If AI is to truly enter the physical world, Korea is an ideal testbed.

It has dense cities, strong manufacturing, a powerful electronics industry, an advanced automotive supply chain, mature telecommunications infrastructure, and an industrial culture in which large corporate groups can quickly push new technologies into deployment.

Hyundai Motor has been an official major partner of FIFA since 1999 and has served as the official automotive brand of the FIFA World Cup for seven consecutive tournaments. During the 2026 FIFA World Cup in North America, Hyundai is not only launching a global promotional campaign but also deploying a large-scale mobility fleet consisting of nearly 1,500 passenger vehicles and buses.

Its key partnerships and marketing initiatives include:

Mobility fleet support: Across the 16 host cities in the United States, Canada, and Mexico, Hyundai will provide transportation services for national teams, officials, and media representatives.

Robotics technology showcase: As FIFA’s official robotics partner, Hyundai will deploy Boston Dynamics’ Spot robots at tournament venues for autonomous patrols and real-time monitoring.

From Taiwan to Korea: NVIDIA Is Connecting Asia’s AI Industrial Chain

The fact that Huang visited Taiwan first and then Korea says a great deal about the real map of NVIDIA’s AI supply chain.

Taiwan is the core hub of AI hardware manufacturing.

TSMC provides advanced process technology and CoWoS. Foxconn, Quanta, Wistron, Wiwynn, Inventec, and others handle AI servers and rack integration. Delta Electronics provides power and thermal solutions. Taiwan’s PCB, CCL, connector, mechanical-component, and cooling supply chains support the entire AI infrastructure stack.

Korea controls high-end memory, consumer electronics terminals, automobiles, robotics, and internet platforms.

These two countries are not substitutes for each other. They are highly complementary.

One can understand it this way:

Taiwan makes AI compute possible.
Korea gives AI memory, applications, and a path into factories, vehicles, and everyday life.

As NVIDIA evolves from a GPU company into an AI infrastructure company, it needs more than chip manufacturing. It needs a complete national-level supply chain.

Taiwan provides manufacturing and system integration. Korea provides memory and industrial applications. Japan provides materials, equipment, and precision components. The United States provides architecture, software, cloud platforms, and capital expenditure.

This is the new Asian division of labor in the AI era.

Korea’s Anxiety: It Cannot Stop at HBM

Korea is important in AI, but it also faces obvious pressure.

• First, HBM is critical, but ultimate system-level control still belongs to platform companies such as NVIDIA. If Korean companies only provide memory, they may still be trapped in a structure of high capex, strong cycles, and high customer concentration.

• Second, Samsung still faces challenges in advanced logic foundry and AI accelerator manufacturing. If Korea wants to become a complete AI semiconductor powerhouse, it cannot rely solely on memory. It must also make breakthroughs in foundry, advanced packaging, EDA/IP, ecosystem development, and AI ASICs.

• Third, although Korea has internet platforms and AI model companies such as Naver, it still lags behind U.S. hyperscale cloud platforms in capital expenditure and global reach. This means Korea needs a clearer sovereign AI strategy.

• Fourth, while robotics is Korea’s next opportunity, the real difficulty lies in the software stack, data flywheel, sensors, control systems, simulation platforms, and large-scale deployment.

Korea has hardware manufacturing advantages, but it still needs long-term investment to turn manufacturing strength into AI robotics platforms.

This is why Huang’s popularity in Korea also contains a sense of anxiety. Korea knows it is important, but it also knows that the rules of competition in the AI era are changing.

In the past, Korea excelled at making single products globally dominant, such as DRAM, NAND, OLED, smartphones, and televisions. But AI-era competition is about system-level integration, platforms, ecosystems, and full-chain capabilities from data centers to end devices.

For Korea, this is both an opportunity and a challenge.

Conclusion: Korea Is Not Chasing Jensen Huang. It Is Chasing Its Own AI Future

Jensen Huang being chased across Korea may look like a technology celebrity phenomenon. But what Korea is really chasing is its own AI future.

Koreans understand that AI is not just the next smartphone cycle, nor merely another memory upcycle. It is a reordering of the industrial hierarchy.

Whoever enters the core supply chains of NVIDIA, OpenAI, Microsoft, Google, Amazon, Meta, and other AI giants will capture the next decade of capital expenditure. Whoever can bring AI into manufacturing, automobiles, robotics, and end devices will turn compute into real industrial productivity.

That is why Jensen Huang’s Korea visit became a national event.

Grilled pork belly, chimaek, Faker, Yoo Jae-suk, and the KBO first pitch all looked like lighthearted cultural activities. But in essence, together they formed a highly successful exercise in AI supply chain diplomacy.

Jensen Huang did not come to Korea merely to eat barbecue, drink beer, dance, and throw a baseball.

He came to tell Korea:

You are not just NVIDIA’s suppliers.
You are important partners in the age of AI industrialization.

And through this wave of “Jensen Mania,” Korea also showed the world that it is not merely a memory powerhouse. It is an indispensable national platform as AI moves from data centers into the physical world.

NAVER Expands AI Infrastructure With NVIDIA to Serve Surging Global AI Demand

• NAVER, an AI Cloud, will build AI factories on the NVIDIA DSX platform at gigawatt scale, starting with AI infrastructure expansion at GAK Sejong.

• NVIDIA DSX gives NAVER a proven AI factory blueprint to serve Korea’s industries and global AI cloud customers as demand for useful AI surges at lowest token cost.

• NAVER will use NVIDIA full-stack AI platforms, models and software to advance regional AI models including next-generation HyperCLOVA X models, its Seoul World Model development and agentic AI services.

Korea’s AI Boom Is Creating a Two-Speed Economy

South Korea’s economy is increasingly becoming a two-speed story. In May, exports surged 53.2% year over year to a record $87.75 billion, with a trade surplus of $26.95 billion—the fastest growth since 1984. But the boom is being driven almost entirely by one sector: AI semiconductors. As the home of Samsung and SK hynix, Korea is becoming one of the biggest beneficiaries of the global AI infrastructure arms race, with semiconductor exports reaching $37.16 billion in May, nearly tripling from a year earlier and exceeding $30 billion for the third straight month. Computer-related exports also jumped nearly fourfold. Yet traditional industries are moving in the opposite direction: auto exports fell 5.9%, steel declined 2.1%, and exports to the Middle East dropped 7.7% amid geopolitical tensions. The message is clear: Korea’s AI supply chain is overheating, but much of its old manufacturing economy is not sharing the same momentum.

Jia Choi: Korean Fried Chicken is a must-have dish when it comes to Korea. It is light and crispy with a thin, almost paper like skin, and inside is moist and tender. I simplified the recipe so that you can make the taste of a chicken restaurant at home.

At Computex 2026, Lightmatter founder and CEO Nick Harris delivered a message that is becoming increasingly difficult for the AI infrastructure industry to ignore: the next major bottleneck in AI is no longer raw compute. It is interconnect.

This may sound like a photonics company making the case for photonics, but the structural logic is much deeper. Over the past decade, the semiconductor industry has focused on bigger GPUs, more advanced process nodes, higher HBM bandwidth, and larger AI clusters. But as models move into the trillion-parameter era, and as Mixture-of-Experts architectures, long-context inference, prefill/decode separation, and multi-rack training become mainstream, the central challenge is no longer whether a single accelerator is fast enough.

The real question is whether thousands — eventually tens of thousands — of XPUs can operate as one giant distributed brain.

That is the core of Lightmatter’s argument: AI scaling has become an interconnect problem.

AI Growth Has Outpaced the Power and Network Foundation

AI workloads are growing explosively. Training requires huge amounts of synchronous communication. Inference is increasingly constrained by time-to-first-token, decode latency, memory bandwidth, KV cache movement, and network hop count.

This is especially obvious in MoE models. MoE allows AI models to scale parameter count without activating the full model for every token, but it also creates a much more complex communication pattern. Tokens need to move between experts, accelerators, racks, and memory pools. The more distributed the model becomes, the more the network determines the real system performance.

In other words, the bottleneck is shifting.

Previously, the industry asked: how powerful is the GPU?

Now the more important question is: can data move quickly, efficiently, and predictably to the right accelerator at the right time?

This is why Lightmatter frames optical interconnect not as a replacement for existing optics, but as a new infrastructure layer for AI systems. The value is not simply higher bandwidth. The value is higher GPU utilization, lower latency, lower power per bit, and better system-level scalability.

In the AI factory era, the winning metric will not only be FLOPS. It will be tokens per watt, tokens per second per dollar, and the ability to keep a massive distributed compute system fully utilized.

Training, Prefill, and Decode Are Three Different Bottlenecks

One of the most important points in Lightmatter’s presentation was the separation of AI workloads into three categories:

Training, inference prefill, and inference decode.

These workloads may all run on AI accelerators, but they stress infrastructure in very different ways.

Training is dominated by collective communication. Large GPU clusters need to synchronize gradients, exchange intermediate results, and maintain parallel efficiency across many devices. If the network cannot keep up, expensive GPUs sit idle waiting for data.

Inference prefill is dominated by time-to-first-token, or TTFT. For chatbots, enterprise agents, coding assistants, and real-time AI applications, the user experience is strongly shaped by how quickly the first token appears.

Inference decode is different again. Decode is often latency-sensitive, memory-intensive, and highly dependent on KV cache access. As context length increases, decode becomes more constrained by memory movement and interconnect latency.

This is why Lightmatter argues that optical interconnect can improve the entire AI workload curve, not just peak bandwidth. According to the presentation materials, Passage can help reduce training time by around 3 times, reduce TTFT by around 3 times, and improve decode interactivity by around 11 times.

The exact numbers matter, but the bigger message matters more: photonic interconnect is moving from a networking component into a system-level AI performance component.

Passage Is Not Just an Optical Module. It Is a Photonic Interposer

Lightmatter’s central platform is Passage. Many people may initially classify it as CPO or an optical module, but that understates the ambition.

Passage is better understood as a photonic interposer architecture. It brings optics into the package-level and system-level fabric of AI computing.

In traditional architectures, chip I/O is constrained by the edge of the die. This is often described as the shoreline problem. A chip is like an island: all external connections must pass through the coastline. As chips become larger and data movement becomes more intense, the edge becomes a bottleneck.

Passage attempts to break this limitation by moving optical I/O deeper into the package and across the die complex. Instead of relying only on the chip edge, photonic interconnect can be placed much closer to where data is generated and consumed.

This is the key difference between conventional pluggable optics and Lightmatter’s architecture.

• Pluggable optics sit outside the system.

• CPO brings optics closer to the switch or accelerator.

• A photonic interposer makes optics part of the AI compute fabric itself.

That is why Passage M1000 is positioned as a photonic superchip, not merely an optical engine. The product includes 114 Tbps of bandwidth, 1,024 SerDes, a large photonic interposer, built-in optical circuit switching, and a packaging concept designed for high-density AI systems.

The implication is clear: optical interconnect is entering the same strategic layer as advanced packaging, HBM integration, silicon interposers, and AI accelerator architecture.

From Scale-Up and Scale-Out to Scale-Across

Lightmatter also divides future AI interconnect into three expansion domains.

Scale-up refers to short-distance interconnect, usually inside a rack or pod, around the one-meter level.

Scale-out refers to interconnect across racks or rows in the data center, around the 100-meter level.

Scale-across refers to much longer-distance interconnect across data centers or AI campuses, potentially 10 kilometers or more.

Copper still has advantages at very short distances. But as data rates increase, copper faces worsening insertion loss, crosstalk, retimer power, connector complexity, and PCB material constraints. At 224G and beyond, the cost of keeping electrical signaling alive rises sharply.

This is where optics becomes structurally important.

The point is not that optics will replace copper everywhere. The point is that optics will take over the high-bandwidth, high-density, low-latency, and longer-reach portions of the system where copper becomes too power-hungry or too complex.

Future AI infrastructure will likely become a hybrid system: copper remains relevant inside tightly coupled packages and boards, while optics expands from rack-to-rack networking into scale-up domains, CPO, NPO, and eventually photonic interposers.

NPO, CPO, and Photonic Interposer: The Roadmap Is Becoming Clear

Lightmatter’s roadmap reflects three levels of optical integration.

• The first level is NPO or optics-near-package. This brings optical connectivity closer to the XPU or switch ASIC, but does not fully embed optics into the package architecture. Passage L20 fits into this direction and is designed as a general optical interconnect product for NPO, CPX, and XPO applications.

• The second level is CPO, or co-packaged optics. Here, optics moves much closer to the switch or accelerator silicon. This reduces electrical reach, lowers power, and increases bandwidth density.

• The third level is the photonic interposer, represented by Passage M1000. This is the more radical architecture. Optics is not only near the chip. It becomes part of the chiplet and package fabric.

This roadmap is very important for the semiconductor supply chain because it collapses several previously separate industries into one system problem.

Advanced packaging, silicon photonics, SerDes, optical fiber arrays, external laser sources, liquid cooling, OSAT assembly, wafer-level testing, interposer manufacturing, and data center serviceability all become connected.

For Taiwan, this is especially relevant. The island already plays a central role in foundry, advanced packaging, substrates, AI servers, liquid cooling, and system integration. If photonic interposers and CPO move into volume production, Taiwan’s role in AI infrastructure could move even deeper — from assembling AI servers to building the optical nervous system of AI factories.

Guide: Laser Sources Become AI Infrastructure Components

Another important product in Lightmatter’s portfolio is Guide, which the company positions as part of its very large scale photonics strategy.

This matters because if every AI cluster requires massive optical I/O, then laser sources themselves become a bottleneck. Traditional systems rely on many pluggable optics and distributed lasers, but this creates faceplate congestion, thermal complexity, maintenance burden, and many potential failure points.

Guide takes a different approach. It centralizes high-density laser sources into a liquid-cooled laser platform designed to support co-packaged optical systems.

The strategic message is simple: light generation is becoming an infrastructure layer.

In the past, lasers were treated as components inside optical modules. In the future, high-density external laser sources may become shared resources in AI systems, similar to how power shelves, cooling loops, and switch fabrics are treated as infrastructure.

This shift will create new requirements for thermal design, laser reliability, wavelength stability, optical coupling, field replacement, and system-level monitoring.

For the supply chain, this means that laser packaging, thermal interface materials, precision alignment, micro-optics, liquid cooling, and reliability testing will become more important.

eClick and vClick: Solving the Serviceability Problem of CPO

One of the biggest barriers to CPO adoption has always been serviceability.

Pluggable optics are attractive because they are easy to replace. If a module fails, the operator can remove it and install a new one. But when optics are integrated closer to the ASIC or package, the maintenance model becomes more difficult.

If an optical connection fails, does the whole expensive switch or accelerator package need to be replaced?

This question has limited the pace of CPO deployment.

Lightmatter: We has announced vClick™ Optics, the first Advanced Packaging compatible dFAU for high-bandwidth Co-Packaged Optics, ensuring high production yield and field serviceability. This breakthrough includes support for pluggable DWDM fiber with an insertion loss of less than 1.5 dB. We are proud to work with SENKO Advanced Components, Inc. and ASE Global on innovative solutions that enable massively deployable and serviceable Passage 3D photonic interconnects.

Lightmatter’s eClick and vClick are designed to address this issue by providing removable optical fiber array units compatible with advanced packaging. The goal is to preserve the density benefits of co-packaged optics while maintaining a realistic field-service model.

This is a major point. CPO cannot scale only by showing better bandwidth or lower power. It must also prove that hyperscalers can operate, maintain, and repair these systems at data center scale.

In that sense, eClick and vClick are not just connector technologies. They are part of the economic foundation required for CPO deployment.

The key advantages of vClick include:

• High-bandwidth DWDM compatibility: Supports broadband coarse wavelength division multiplexing (CWDM) and dense wavelength division multiplexing (DWDM) over a wide optical spectrum of up to 80+ nm, enabling large-scale optical bandwidth density and flexibility.

• Advanced packaging compatibility: The technology is compatible with mold-and-grind advanced packaging process flows used by major global foundries and outsourced semiconductor assembly and test providers (OSATs).

• Automated assembly: No active fiber alignment is required during production, helping reduce assembly and testing time.

• Field serviceability: With measured insertion and repeated mating losses below 1.5 dB, vClick can preserve the optical power budget required for field-serviceable CPO systems supporting bandwidths above 100 Tbps.

BiDi and DWDM: Fiber Economy Becomes Data Center Economy

Lightmatter also emphasizes bidirectional optical technology, or BiDi.

At small scale, fiber count may look like a cabling issue. At AI data center scale, it becomes an economic issue.

A 512-XPU or 1,024-XPU system can require enormous numbers of fibers and connectors. Every additional fiber increases installation complexity, service cost, space requirements, and potential failure points.

BiDi allows transmit and receive signals to share optical infrastructure more efficiently. Combined with DWDM, it can reduce fiber count and improve bandwidth density.

This is why the future of AI networking will not be determined only by lane speed. It will also be determined by fiber efficiency, connector reliability, optical alignment, wavelength management, and total installed network cost.

In large AI factories, optical architecture is not just a performance decision. It is a data center economics decision.

Why Radix Matters: Power, Performance, and Cost Savings

Lightmatter BiDi technology doubles the radix of a network switch without increasing the number of optical fibers in the network. A higher radix, as illustrated above, reduces the number of hops a data packet must take to cross the network. Fewer hops mean fewer switches are needed for a given bisection bandwidth—enabling lower hardware costs and reduced power consumption. Put another way, increased radix (and bandwidth) enables larger, higher performing AI compute clusters without a corresponding increase in the number of switch tiers in their network. A network with fewer switch nodes inherently consumes less power.

Finally, fewer hops translate directly into lower end-to-end latency and greater predictability. For tightly-coupled AI training workloads where GPUs are in constant communication, minimizing this latency is paramount for maximizing the overall computational efficiency. Specifically for Mixture-of-Experts (MoE) models, a higher radix allows expert parallel communications to remain within the high-bandwidth domain, preventing them from being bottlenecked by slower scale-out networks. This enables MoE models with a larger number of experts and finer-grained expert configurations, which are crucial for increasing model capacity and achieving faster training times.

From a SerDes-Centric World to a Photonics-Centric World

For many years, high-speed interconnect has been SerDes-centric. The industry has competed on faster electrical lanes, better equalization, better retimers, lower bit error rate, and stronger signal integrity.

SerDes will remain critical. But the center of gravity is changing.

As data rates continue to rise, relying only on stronger SerDes, more retimers, more complex PCB materials, and higher-end connectors becomes increasingly expensive. At some point, the system has to move the optical boundary closer to the compute boundary.

That is the transition Lightmatter is betting on.

The industry is moving from using optics as a long-distance transport layer to using optics as an architectural layer for AI computing.

This is the real meaning of optical infrastructure.

Lightmatter’s 3D photonics ecosystem

For hyperscale AI infrastructure, centered around its Passage™ CPO platform. Rather than positioning Passage as a standalone optical interconnect product, Lightmatter presents it as a full supply-chain ecosystem that combines custom ASIC partners, SerDes electrical IC partners, photonic IC partners, detachable fiber array unit suppliers, and its Guide® VLSP™ light engine. The key message is that scaling AI infrastructure now requires a tightly integrated photonics and advanced packaging platform, where optical connectivity, electrical signaling, packaging, and fiber attach are co-designed for high-volume deployment.

March 11, 2026 - Lightmatter announced a major milestone for AI optical interconnects, demonstrating its Passage™ Co-Packaged Optics chiplet with a record 1.6 Tbps throughput per fiber. The platform uses a 16-wavelength DWDM architecture with 112G SerDes lanes, delivering up to 8x higher bandwidth per fiber than existing NPO and CPO solutions.

By combining Lightmatter’s Passage photonic engine with Qualcomm Technologies’ 112G PAM4 optical SerDes chiplet, the company is positioning its technology as a high-volume-ready CPO architecture for hyperscale AI data centers. The key significance is not only higher bandwidth density, but also lower fiber count, reduced cabling complexity, better power efficiency, and a clearer path toward 100 Tbps and beyond per package for next-generation XPUs and switches.

Conclusion: The Next Foundation of the AI Factory Is Optical

The key message from Lightmatter’s Computex 2026 presentation can be summarized in one sentence:

The next bottleneck in AI is not only compute. It is interconnect. And the next generation of interconnect will increasingly be optical.

From Passage M1000 and photonic interposers, to L20/L200 for NPO and CPO, to Guide laser platforms, BiDi, DWDM, eClick, and vClick, Lightmatter is not building a single component. It is building an optical infrastructure stack for AI factories.

If NVIDIA defines the GPU and rack-scale computing layer of the AI factory, Lightmatter wants to define how data moves inside that factory.

This has major implications for the semiconductor industry.

The future AI data center will not be won only by buying more GPUs. It will be won by connecting those GPUs into a more efficient, lower-latency, lower-power, and more scalable system.

In that system, photonics is no longer just a supporting technology.

It is becoming the nervous system of AI infrastructure.

Lightmatter LinkedIn: The scale-up wall is real. To solve it, we’re integrating our industry-leading photonic interconnects into the ecosystem where it matters most. We are thrilled to announce that Lightmatter has become an optics partner in the NVIDIA NVLink™ Fusion ecosystem.

Scaling AI means scaling interconnects. As frontier models grow relentlessly, electrical interconnects are hitting fundamental physical limits on power, reach, and density, leaving massive amounts of compute capacity underutilized. Photonics is the only path forward.

Through this integration with NVIDIA's advanced system architecture, custom and semi-custom accelerators will connect to NVIDIA switch silicon via our Passage® co-packaged optics (CPO) and near-packaged optics (NPO)—powered by our Guide® VLSP™ lasers and industry-first bi-directional technology. This enables hyperscale customers to build AI factories with purpose-built silicon, unified by the highest bandwidth, lowest power optical fabric available from Lightmatter.

This is what we’ve been building toward since day one: empowering multi-rack scale-up clusters with the industry’s most advanced photonic interconnects, accelerating frontier AI model training and inference to unprecedented speeds.

AI data centers are entering a new power era. As GPU clusters scale from tens of kilowatts per rack toward hundreds of kilowatts, and eventually megawatt-class rack systems, the bottleneck is no longer only compute, memory, or networking. It is power delivery.

Traditional data center power architectures were designed for a very different workload profile. The conventional path—medium-voltage AC input, multiple AC/DC and DC/DC conversion stages, UPS systems, power shelves, busbars, and finally low-voltage delivery to the server—worked reasonably well when rack power stayed below 30–60 kW. But AI infrastructure is now pushing far beyond that range. In this environment, every conversion stage, every copper busbar, every thermal loss, and every square meter of power-room space becomes a strategic constraint.

This is why the industry is moving toward 800V high-voltage direct current architecture, or 800V HVDC, with the solid-state transformer, or SST, emerging as one of the most important enabling technologies.

The Rise of the 800V HVDC ArchitectureSurging Power Consumption in AI Data Centers

The rapid increase in AI server power consumption is being driven by the sharp rise in GPU computing performance. For example, the power demand of NVIDIA’s GB200/GB300 server racks has already exceeded 200 kW. Future 1 MW-class Kyber racks will consume even more electricity.

Under the traditional 54V power distribution architecture, a single 1 MW rack would require approximately 200 kg of copper busbars. If this model were applied to a GW-scale data center, copper consumption could reach as high as 500,000 tons, which is clearly unsustainable.

In addition, repeated AC/DC and DC/DC conversion stages increase line losses, making the traditional architecture increasingly inefficient. As a result, the industry needs a power delivery solution with higher voltage, lower current, fewer conversion stages, and better adaptability to high power density.

Advantages of High-Voltage DC Architecture

High-voltage DC power distribution raises the supply voltage from the traditional 48V/54V level to ±400V or 800V DC.

According to NVIDIA’s white paper released at GTC 2025, an 800V HVDC architecture can use solid-state transformers and industrial-grade rectifiers at the edge of the data center to directly convert 13.8 kV AC power into 800V DC.

This architecture requires only two conductors to deliver 800V power into IT racks. Inside the rack, DC/DC modules then step the voltage down to 50V or lower for GPU power delivery.

Because the system operates at a higher voltage, the required current is reduced. This can significantly lower copper weight, by roughly 45%, while also reducing line losses and heat generation.

In addition, by reducing the number of AC/DC and DC/DC conversion stages, the architecture can improve end-to-end power delivery efficiency by around 5%.

Below we will share:

• Limitations of Traditional HVDC and the 800V Breakthrough

• The Role of the Solid-State Transformer (SST)

• Advantages of SST

• SST Cost Structure

• Development Stages and Adoption Timeline

• Key Suppliers and Strategies

• Supply Chain Structure

• Challenges and Future Outlook

Read more

On June 1, 2026, Jensen Huang stepped onto the stage at the Taipei Music Center. His opening line — “Very good to be home” — immediately electrified the audience.

But if we treat this GTC Taiwan Keynote merely as another product launch, we underestimate its significance.

This was, in essence, a strategic declaration that the AI factory era has officially arrived. Huang was not simply saying that a new GPU is faster or that a new rack is more powerful. He was explaining that the business model, manufacturing logic, and supply-chain structure of AI infrastructure are being fundamentally redefined.

In the past, data centers were viewed as cost centers. Companies bought servers, GPUs, electricity, and facilities. At their core, these investments were treated as IT infrastructure expansion.

But in Huang’s new narrative, AI data centers are no longer just “server rooms.” They are a new form of industrial production unit. They do not produce steel, cars, or chips. They produce tokens.

In other words, the AI factory of the future converts electricity, chips, networking, cooling, software, and models into tokens that can be priced, sold, and monetized.

That is the most important underlying logic of the entire keynote.

Token Economics: Compute Is No Longer a Cost — It Is a Revenue Engine

One of the most striking numbers Jensen Huang presented was the economic model of a 1GW AI data center.

If a 1GW AI data center upgrades from the Blackwell generation to the Vera Rubin generation, while also adopting a more efficient inference architecture, its annual revenue potential could rise from roughly US$30 billion to US$300 billion.

This is not merely a hardware performance upgrade. It is a transformation in business logic.

In the past, when enterprises bought GPUs, they asked: How much does this card cost? How many years will it depreciate over? How much electricity will it consume?

In the AI factory era, the questions become: How many tokens can each watt of power generate? How much revenue can each token create? How quickly can the capital expenditure of the entire data center be recovered?

This is what Huang means by token economics.

Under this framework, GPUs are no longer just hardware devices. They are revenue machines. Data centers are no longer just infrastructure. They are factories with productive output. Every kilowatt-hour of electricity, every GPU, every NVLink connection, every optical module, and every PCB ultimately needs to be converted into token capacity.

Therefore, “the more you buy, the more you earn” is not just a marketing slogan. It is a capital expenditure logic.

As long as model demand continues to grow, inference workloads continue to expand, and token output per watt continues to improve, investment in AI data centers will shift from a cost burden into a profit engine.

This is also why NVIDIA is redefining itself from a GPU company into an AI infrastructure company.

Agentic AI Has Arrived: AI Is Moving from Tool to Worker

The second major theme of Huang’s keynote was agentic AI.

Over the past two years, the market has focused mostly on generative AI. Users enter prompts, and AI generates text, images, code, or reports. This generation of AI is still largely about answering questions.

Agentic AI is different.

It does not merely answer. It can understand goals, break down tasks, observe its environment, call external tools, execute workflows, and complete complex jobs.

This means AI is evolving from a “tool” into a “worker.”

Huang used software development as an example.

AI has not made engineers irrelevant. Instead, it has significantly increased software output. When AI amplifies the productivity of engineers, companies have even more reason to invest in additional development resources, because each engineer can now generate far greater leverage.

This point is critical.

The true value of AI is not about removing people. It is about increasing the density of human output.

In the past, one engineer could complete only a limited amount of code in a day. In the future, that same engineer may use AI agents to manage multiple development workflows at once.

In the past, one researcher could read only a limited number of papers. In the future, an AI agent can first perform data collection, comparison, summarization, and preliminary reasoning.

In the past, enterprise workflows required multiple systems, multiple departments, and multiple people to connect manually. In the future, AI agents may connect these processes directly.

That is the real meaning of agentic AI.

It is not an upgrade to chatbots. It is an upgrade to the enterprise productivity architecture.

Once AI begins to acquire the ability to act, data center demand will shift from training to inference, from single queries to long-running workflows, and from single-model outputs to multi-agent collaboration.

This will drive structural growth in token consumption.

DSX AI Factory: NVIDIA’s Biggest Strategic Transformation

If token economics is the commercial narrative, and agentic AI is the source of demand, then the DSX AI Factory Ecosystem is the strategic backbone that allows NVIDIA to turn this demand into reality.

Jensen Huang officially launched the NVIDIA DSX AI factory ecosystem, making it the most important product-level strategy of the keynote.

The core meaning of DSX is that NVIDIA is no longer just selling GPUs, nor even just selling racks. It is now offering a methodology for building AI factories.

This methodology covers three stages of the AI factory lifecycle:

First, design.
Second, deployment.
Third, operation.

In the past, these three stages were often fragmented. Data center builders handled civil engineering and power. Server makers handled racks. Chip companies provided GPUs. Networking companies supplied switches. Cooling vendors managed liquid cooling. Software teams then tried to integrate everything afterward.

The problem is that an AI factory is not a traditional data center.

Its power density is higher. Its signal transmission is more complex. Its cooling pressure is greater. Its system-integration difficulty is much higher. GPUs, CPUs, NVLink, optical interconnects, liquid cooling, power systems, mechanical parts, PCBs, connectors, and software scheduling must be co-designed from the beginning.

This is where DSX creates value.

DSX is not a single product. It integrates open-source software libraries, APIs, reference designs, accelerated computing platforms, and supply-chain technologies into one AI factory co-design platform.

Its three key pillars are:

• First, DSX Sim Omniverse.
  Before physical construction begins, the entire AI factory can be simulated through a digital twin. Power, networking, liquid cooling, rack configuration, and chip integration can be validated in advance to reduce construction risk.

• Second, DSX OS.
  Once the AI factory is powered on, DSX OS manages operations and converts massive hardware infrastructure into schedulable, manageable, and optimizable AI compute capacity.

• Third, DSX Max LPM.
  Within the same power envelope, more GPUs can be safely deployed, increasing token output per watt and enabling data center operators to generate higher revenue without expanding their power budget.

This means NVIDIA is turning AI factories from “hardware stacking” into “system engineering.”

More importantly, DSX allows NVIDIA to close the full loop from planning and construction to operation.

This is a major shift.

When NVIDIA controls the design standards of AI factories, it is no longer just a chip supplier. It becomes the architecture-defining company for the entire AI infrastructure stack.

Vera Rubin Enters Full Production: AI Racks Enter the Super-System Era

Another key focus of the keynote was the full production rollout of the next-generation rack-scale supercomputer, Vera Rubin.

Huang revealed that Vera Rubin is one of the largest engineering projects in NVIDIA’s history, involving as many as 40,000 engineers. The entire platform contains up to six trillion transistors.

Behind this number is not just a more powerful chip, but a new level of complexity for the entire AI system.

In the past, semiconductor competition mainly centered on the chip itself. Who had the most advanced process? Whose GPU die was larger? Whose HBM bandwidth was higher?

But in the Vera Rubin generation, competition is no longer confined to the chip level. It has expanded to the full rack system.

GPUs must be co-designed with CPUs, HBM, NVLink, switches, optical modules, power modules, liquid cooling systems, PCB backplanes, and mechanical structures. If any link fails, the output efficiency of the entire AI factory is constrained.

This is why Taiwan’s supply chain has become strategically more important.

TSMC provides advanced process technology and CoWoS packaging.
Foxconn, Quanta, Wistron, and Wiwynn handle full-rack system integration.
Delta plays a key role in power and thermal solutions

Huang mentioned that NVIDIA is already working with 150 supply-chain partners in Taiwan.

That statement carries deep significance.

Taiwan is no longer simply “manufacturing on order.” It has been deeply embedded into the co-design system of AI factories. From chips to packaging, from motherboards to backplanes, from thermal systems to power delivery, from mechanical parts to full-rack assembly, Taiwan’s supply chain has become an indispensable part of NVIDIA’s AI infrastructure expansion.

Taiwan’s Supply Chain Upgrade: From Manufacturer to Co-Designer

The most important implication of this keynote for Taiwan’s technology industry is the change in Taiwan’s role.

In the past, Taiwan’s position in the global technology industry was very clear: a high-efficiency manufacturing base.

TSMC handled wafer foundry.
ODMs handled server and PC assembly.
PCB, thermal, power, connector, and mechanical-component suppliers provided key parts.

But in the AI factory era, this division of labor is changing.

AI systems are now too complex to be built through a traditional linear supply chain. In the past, brand companies designed and suppliers executed. In the future, chip companies, cloud service providers, system makers, materials suppliers, power vendors, thermal companies, and PCB makers will all participate in the design process.

This is co-design.

In an AI rack, power efficiency affects GPU deployment density. Thermal capability affects clock speed and reliability. PCB materials affect high-speed signal integrity. Connectors and mechanical parts affect rack maintainability and reliability. Packaging capability determines chip bandwidth and yield.

Therefore, the value of Taiwan’s supply chain is no longer just about being cheap, fast, and reliable. It is about whether Taiwanese companies can participate in engineering decisions early in the system-design process.

This changes the valuation logic.

In the past, the market often valued Taiwanese hardware companies through the framework of contract-manufacturing margins.

But if Taiwanese companies increasingly enter the co-design layer of AI factories, their order stickiness, product cycles, technical barriers, and pricing power will all look very different.

As Vera Rubin, Rubin Ultra, and future platforms continue to advance, Taiwan’s supply chain will increasingly resemble an “engineering community” for AI infrastructure, rather than a group of ordinary component suppliers.

AI PC: Microsoft and NVIDIA Redefine Personal Computing

Beyond AI factories, Huang also discussed the next stage of AI PCs.

He noted that Microsoft and NVIDIA have spent the past three years jointly redesigning how PCs operate, turning PCs from devices that merely run traditional applications into new computing platforms with AI agent capabilities.

This means the interaction model of PCs will change.

In the past, using a computer meant opening software, clicking menus, entering text, and manually completing tasks.

In the future, using a computer may mean directly describing intent, while AI understands files, reads data, generates code, performs analysis, and produces output.

The PC will evolve from a “collection of tools” into a “personal AI workstation.”

This is also why NVIDIA’s collaboration with MediaTek on Arm-based AI PC chips has drawn market attention. If N1X lands successfully, it will represent NVIDIA’s further expansion from data centers, robotics, and automotive platforms into personal AI computing.

The strategic significance is that AI will not exist only in the cloud. The future AI architecture will be a combination of cloud, edge, PC, and end devices.

AI factories will handle large-scale training and high-density inference.
AI PCs will handle personalized agents, data privacy, and local computing.
Edge AI will handle real-time sensing, low-latency control, and field applications.

Together, these layers will form a new AI computing network.

NVIDIA Constellation Taipei Headquarters: Taiwan’s Strategic Role Moves Higher

Huang’s announcement of the official opening of NVIDIA Constellation’s Taipei headquarters also carries strong symbolic importance.

This is not merely the opening of an office. It is the concrete expression of NVIDIA’s long-term commitment to Taiwan’s supply chain.

By establishing a permanent R&D and collaboration base in Taiwan, NVIDIA is signaling that Taiwan is not only a shipping base. It is part of R&D, design, co-engineering, and supply-chain decision-making.

Before the keynote, Huang invited senior leaders from TSMC, Quanta, Wistron, ASUS, MediaTek, Pegatron, and Foxconn to join him in discussion. That scene itself made one thing clear:

The core battlefield of AI infrastructure cannot operate without Taiwan.

In the future, the rollout of every new NVIDIA platform will depend not only on GPU architecture, but also on whether Taiwan’s supply chain can simultaneously solve the bottlenecks in process technology, packaging, thermal management, power delivery, connectors, PCBs, mechanical parts, and full-rack assembly.

This is a system-level competition.

Whoever can turn chips into racks faster, racks into data centers faster, and data centers into token factories faster will gain the advantage in the AI infrastructure race.

Conclusion: In the AI Factory Era, Taiwan Is Already on Board

The core message of GTC Taiwan 2026 is very clear.

• AI competition has moved from model competition to infrastructure competition.

• GPU competition has moved from single-chip performance to full-rack system efficiency.

• Data center competition has moved from compute accumulation to token economics.

• Taiwan’s role has moved from manufacturing base to co-designer.

This is a new opportunity for Taiwan’s technology industry, but also a new stress test.

An AI factory cannot be built by a single company. It requires full coordination across wafer foundry, advanced packaging, PCBs, power, thermal systems, optical communications, connectors, mechanical parts, ODMs, system integration, and software platforms.

Taiwan’s greatest strength in the past was manufacturing efficiency. But in the future, the real scarce capabilities will be system integration, co-design, and the ability to maintain a strategic position inside the global AI infrastructure stack.

On the surface, Huang’s keynote introduced Vera Rubin, DSX, and AI PCs.

But the deeper message is this: the AI factory era has officially begun, and Taiwan is standing at the center of this new industrial revolution.

The question is no longer whether Taiwan can participate in the AI supply chain.

The real question is whether, as AI factories become the next generation of global infrastructure, Taiwan can move from being a critical supplier to becoming a standard-setter, a system designer, and eventually part of the new industrial order of AI.

That is the real reason GTC Taiwan 2026 deserves to be remembered.

In the AI era, many people are asking the same anxious questions:

What should young people study?
What skills will still matter?
Which jobs will not be replaced by AI?

Jensen Huang’s answer is both simple and profound.

He argues that what you study is not the most important issue. The things that mattered in the past will still matter in the future. AI will change tools, workflows, and industrial structures, but it will not change society’s need for good questions, sound judgment, strong communication, and human understanding.

In other words, the truly scarce talent in the AI era will not be people who merely know how to use AI tools. It will be people who can turn AI into leverage.

That is why, in his interview with CNA, Huang emphasized several abilities that may sound traditional, but will become even more valuable in the age of AI: storytelling, asking questions, sensing imperfection, and understanding the real purpose behind work.

These are not just technical skills. They are ways human beings engage with the world.

AI Lowers the Technical Barrier, but It Does Not Remove the Thinking Barrier

In the past, being able to code, make presentations, edit videos, analyze data, or write professional reports was itself a competitive advantage. These skills required training, practice, and tool familiarity.

Generative AI is now lowering many of those barriers.

People who cannot code can ask AI to help build a website or write a script. People who are not fluent in English can use AI to translate, polish, and rewrite. Tasks that once required hours or days to produce a first draft can now be completed in minutes.

What does this mean?

It means execution is being commoditized.

Execution is still important. But simple execution is no longer as scarce as it used to be. The real differentiator will be whether you know what problem you are trying to solve, whether you can give the right instructions, and whether you can judge whether the AI-generated answer is actually useful.

AI lowers the technical barrier, but it does not lower the thinking barrier. In many ways, it raises it.

When everyone can generate content quickly, the real question becomes: Does your output have direction? Does it have judgment? Does it have a point of view? Does it hit the core issue?

That is the deeper meaning behind Huang’s view that what mattered in the past will still matter in the future.

Storytelling: In the AI Era, Communication Is Not Decoration. It Is Leverage.

The first ability Huang emphasized is storytelling.

Many people think storytelling is just marketing language or surface-level packaging. But in the technology industry, storytelling is much deeper than that. It is the ability to translate complex systems into a direction that others can understand, believe in, and participate in.

This will become even more important in the AI era.

AI is making information abundant, content cheap, and data easy to access. When everyone can generate reports, slide decks, articles, images, and videos, the market will become even more short of people who can build a coherent narrative.

A good story is not about making something sound beautiful. It is about turning chaotic information into a clear logical structure.

The semiconductor industry offers a good example. Advanced nodes, advanced packaging, HBM, CPO, glass substrates, AI servers, and power architecture are all complex topics. But the people who truly shape market understanding are not only those who know every technical detail. They are the ones who can place those technologies into a larger industrial framework.

Why is NVIDIA important?

Not simply because it is a GPU company, but because it has redefined AI infrastructure.

Why is TSMC important?

Not simply because it is a foundry, but because it has become the physical convergence point of global AI capital expenditure.

Why is advanced packaging important?

Not because packaging suddenly became fashionable, but because as Moore’s Law slows, system-level integration has become the next battlefield for compute scaling.

This is the power of storytelling.

Storytelling is not a liberal arts skill or an engineering skill. It is the ability to integrate knowledge, logic, emotion, perspective, and direction. AI can help write sentences, but it does not automatically know which narrative line truly matters.

In the future, people who can tell the right story will be more valuable than people who merely possess information.

Asking Questions: The Future Belongs Not to Those with the Most Answers, but to Those with the Sharpest Questions

The second ability is asking questions.

In the AI era, answers are becoming cheaper. The expensive part is the question.

In the past, we used search engines to find answers. You typed in keywords, and the system gave you links. Now AI goes further: it searches, organizes, summarizes, and reasons. This makes answers faster to obtain, but it also means humans must become much better at defining what they are really asking.

Huang used journalists as an example. The best interviewers do not merely prepare many questions in advance. More importantly, they stay in the moment. They listen carefully to what the interviewee is saying, understand what the audience cares about, and make real-time judgments about what to ask next.

This is a highly complex cognitive ability.

It is not about following a list of prepared questions. It is about dynamically adjusting direction in an uncertain conversation.

This ability will become even scarcer in the AI era. AI can answer questions, but humans must define the questions.

For example, if you ask AI, “Analyze NVIDIA,” the question is too broad. AI may give you an article that looks complete but feels generic.

But if you ask, “After NVIDIA shifted from being a GPU company to an AI infrastructure company, what impact will this have on the revaluation of Taiwan’s PCB, power management, thermal, and advanced packaging supply chains?” the question becomes directional.

And if you then ask, “Is this revaluation a one-time valuation expansion, or will it form a structural capital expenditure cycle over the next five years?” the question enters the level of investment analysis and industrial judgment.

People who are powerful in the AI era will not treat AI as a search box. They will treat it as a research assistant, reasoning partner, and opposing analyst. The key is not whether AI can answer. The key is whether you can ask questions that make AI valuable.

Sensing Imperfection: As AI Becomes More Perfect, Humans Must Become Better at Recognizing Reality

Huang also mentioned a fascinating idea: wabi-sabi, the beauty of imperfection.

This point is important.

One of AI’s strongest abilities is producing things that look perfect: polished images, fluent essays, smooth videos, standardized presentations, grammatically correct English, and analysis that appears logically sound.

But the problem is that things that look too perfect can sometimes lose their sense of reality.

As AI-generated content increases, humans will need to become better at identifying what is real, what has texture, what carries human experience, and what reflects judgment formed in the field.

This is especially obvious in industrial analysis.

AI can summarize earnings reports, compare specifications, organize news, and draw trend charts. But it may not sense the imperfect signals inside an industry: supply chain hesitation, customer conservatism, friction in technology adoption, the rhythm of capacity expansion, or the gray zones before yield becomes mature.

Many of the most important judgments exist inside imperfection.

When a new technology is announced, the presentation may look beautiful and the roadmap may look complete. But people who truly understand the industry will ask: When does it enter mass production? Who absorbs the cost? Who is responsible for yield? Is the material supply stable? Are customers willing to redesign? Have standards converged?

These are not questions that a perfect slide deck will voluntarily answer.

In the AI era, humans need to preserve sensitivity to rough reality. They must not be fooled by answers that look complete on the surface. They must be able to see uncertainty underneath.

In the future, judgment will be scarcer than output.

Tasks Can Be Automated, but Purpose Will Not Disappear

When Huang discussed how AI changes work, he used radiologists as an example.

A radiologist’s task is to read medical images. AI can already assist heavily in this area, and in some scenarios it performs extremely well. But the purpose of a radiologist is not merely to read images. The purpose is to diagnose disease, help patients recover, and make responsible judgments inside the medical system.

This distinction is crucial: tasks and purposes are not the same thing.

Many people feel anxious in the AI era because they define their work as a series of tasks.

I organize spreadsheets.
I write reports.
I make presentations.
I reply to emails.
I write code.

If work is defined only as tasks, then yes, it can easily be broken down, automated, or replaced by AI.

• What is harder to replace is understanding the purpose behind the task.

• Why are you organizing this table?

• Who needs this report to make what decision?

• Who is this presentation trying to persuade?

• What relationship is this email trying to build?

• What business problem is this code supposed to solve?

AI can complete many steps, but humans must know where the destination is. The biggest shift in the future workplace is that people must move from being task executors to problem definers and outcome owners.

This will become a major dividing line.

Humans Will Not Lose to AI. They Will Lose to People Who Use AI Better.

One of Huang’s most memorable points is that people will not lose to AI, but they will lose to people who know how to use AI better.

This captures the essence of AI competition.

AI does not simply replace humans. It redistributes the gap between people. If two people were once at a similar level, but one integrates AI into their workflow while the other refuses to use it, the gap between them will widen quickly.

This will not only affect engineers. It will affect analysts, journalists, designers, salespeople, teachers, doctors, lawyers, students, and business leaders.

People who use AI well are not using it merely to be lazy. They are using it to amplify themselves.

They can read one hundred documents instead of ten.
They can complete preliminary research in one day instead of three.
They can build simple tools through natural language even without being professional programmers.
They can generate visual prototypes even if they are not trained designers.

But the key remains the same: humans must know what they want to achieve.

AI amplifies human capability, but it also amplifies human weakness. If you lack judgment, AI may help you produce wrong content faster. If you lack direction, AI may help you get lost in information faster. If you lack taste, AI may help you produce a large amount of mediocre but seemingly complete work.

So the AI era does not mean humans are no longer needed. It means people with direction become more important.

OPTICKS VISION *_*

When Others Use AI to Cut Jobs, Jensen Huang Uses AI to Expand the Future

The AI era has created a strange paradox…

Read more

3 months ago · 5 likes · SEMIVISION

The Core of Education Is Not Avoiding AI, but Learning How to Work with It

For parents, the biggest challenge in the AI era is not banning children from using AI. It is teaching them how to use AI properly.

If AI is treated as a cheating tool, children may become lazy. If AI is treated as an answer machine, children may stop thinking. But if AI is treated as a collaborative partner, it can become a tool for training logic, communication, creativity, and problem-solving.

The real question parents should ask is not, “Should my child be allowed to use AI?”

The better questions are:

Can the child clearly describe an idea?
Can the child ask better questions?
Can the child detect mistakes in AI-generated answers?
Can the child reorganize AI output into an original point of view?
Can the child improve their own thinking through AI feedback?

These are the real basic literacies of the AI era.

Every child should learn how to communicate with AI. This is not just about learning a tool. It is about learning how to turn vague ideas into clear instructions, how to transform inspiration into output, and how to find better questions through imperfect answers.

AI will shift education away from pure memorization and toward the thinking process.

AI Will Not Make Humans Lazy. It Will Make Humans More Ambitious.

Huang’s attitude toward AI is fundamentally optimistic.

He believes that every major technological advance in history did not stop humans from working hard. Personal computers, the internet, smartphones, and cloud computing all made certain things easier. But in reality, they also made human goals larger.

When tools become more powerful, humans do not necessarily become lazy. More often, they begin to imagine doing things that were previously impossible.

This is the real importance of AI.

It does not only save time. It raises the ceiling of human imagination. Work that one person could not do alone in the past can now be done with AI assistance. Projects that small teams could not afford before can now become possible. Cross-disciplinary learning that once took years can now begin much faster.

The greatest danger in the AI era is not that AI is too powerful. It is that humans give up their ambition too early.

If AI is used only to complete minor tasks, it is merely an efficiency tool. But if AI is used to challenge bigger problems, it becomes a capability multiplier.

Conclusion: The Most Important Future Skill Is Remaining Human Beside AI

Jensen Huang’s view of talent is not really about which major is better, nor is it about which single skill guarantees job security.

His real message is that in the AI era, humans must return to what makes them human.

• We need storytelling because people need meaning.

• We need questions because the world is uncertain.

• We need sensitivity to imperfection because the real world will never be as clean as a model output.

• We need to distinguish tasks from purpose because the value of work is not completing steps, but solving problems.

• We need to collaborate with AI because the future is not a competition between humans and AI, but a new era in which humans redefine the boundaries of their own capabilities through AI.

The truly scarce talent of the future will not necessarily be the person who memorizes the most knowledge, nor the person who operates the most tools. It will be the person who can turn AI into an extension of their own ability.

AI will make mediocre output easier to produce. But it will also make excellent thinking more valuable.

The real question is not whether AI will replace you.

The real question is: When AI lifts everyone higher, can you still ask better questions, tell more powerful stories, and preserve the most valuable human imperfection in a machine world that is becoming increasingly perfect?

Huawei’s recent introduction of “Tao Law” naturally draws attention to the phrase “new law.” But from an engineering perspective, the most important part is not the symbol τ itself. What matters is how Huawei is using this symbol to reorganize several post-Moore technology directions into one unified narrative.

The semiconductor industry has always been optimizing time.

The critical path is time. RC delay is time. Memory latency is time. SerDes latency is also time. Over the past several decades, the industry has compressed different layers of time constants by shrinking transistors, increasing frequency, shortening signal paths, improving interconnect materials, and advancing packaging structures.

So the statement that “the next frontier is no longer only scaling transistor dimensions, but scaling system time constants” is not a completely new physical discovery. It is more like a new language framework that reorganizes several things already happening across the post-Moore landscape.

But that does not mean it has no value.

What makes Huawei’s proposal interesting is that it does not stop at the slogan level. In Huawei’s 2026 ISSCC presentation, the narrative moves from geometric scaling to time scaling, and then extends across device, circuit, chip, module, rack, SuperPOD, and data center levels. In the HiONE section, Huawei explicitly lists around 10ns latency, 8Tbps bandwidth, more than 100m distance, built-in light source, and SuperPOD-friendly characteristics. This means Hi-ONE is not an isolated optical module. It is a physical-layer answer to Huawei’s attempt to make an AI system behave more like one large machine.

What is Moore’s Law?

Moore’s Law is the idea that the number of transistors that can fit on an integrated circuit tends to double roughly every two years, with only a minimal increase in cost. It was first proposed by Intel co-founder Gordon Moore in 1965, when he observed that chip complexity was increasing rapidly; in 1975, he revised the pace to a doubling about every two years. In simple terms, Moore’s Law explains why computers, smartphones, and data centers have become dramatically more powerful, smaller, and more energy-efficient over time. It is not a physical law of nature, but an industry roadmap: chipmakers used it as a target to keep improving semiconductor technology. Today, as transistors approach atomic-scale limits, Moore’s Law is no longer only about shrinking chips. It increasingly depends on advanced packaging, new materials, chiplet architectures, and system-level design to keep computing performance moving forward.

Below we will share:

• τ Is a Shared Language for the Post-Moore Era, Not a Huawei-Exclusive Physical Law

• From Logic Folding to System Folding: Huawei Wants to Fold the System

• The First Question for Hi-ONE: Is It CPO or NPO?

• The Second Question: Why Put the Light Source Inside?

• The Third Question: 8Tbps Is Not the Answer. pJ/bit Is the Answer

• Hi-ONE’s Position in the Global Optical Interconnect Spectrum

Read more

NVIDIA CEO Jensen Huang’s latest “trillion-dollar dinner” in Taiwan may look like a gathering of tech industry leaders on the surface. But from a semiconductor and AI infrastructure perspective, it is closer to a live map of Taiwan’s AI supply chain power structure.

From foundry manufacturing, IC design, OSAT, thermal management, power systems, servers, motherboards, ODM assembly, to industrial computers, nearly every critical node of the AI hardware ecosystem appeared in the same room. This was not just a public relations moment. It was a snapshot of how global AI infrastructure is pushing Taiwan back to the center of the technology world.

One Group Photo, One Complete AI Supply Chain

What made this dinner important was not only the six heavyweight Taiwanese tech leaders seated in the front row, but also the executives standing behind them. Together, these companies form the real supply chain behind AI servers and AI data centers.

The second row represents the core of Taiwan’s AI server assembly, system integration, and global delivery capability. From NVIDIA GPU platforms to full rack-scale systems, turning chips into deployable data center hardware is not the work of a single company. It depends on the highly coordinated capabilities of Taiwan’s ODM, EMS, and system integration ecosystem.

The third row covers thermal management, semiconductor packaging and testing, servers, motherboards, and system platforms. It also includes companies that directly interface with cloud customers. In other words, this was not just a dinner photo. It was an AI Factory supply chain layout.

Taiwan Tech Valuation Is No Longer Just a TSMC Story

According to the market cap table cited in the report, TSMC still sits at the top with a market capitalization of about NT$59.51 trillion. It remains the gravitational center of Taiwan’s technology sector.

But the more important point is that the AI wave is now pushing value outward across the entire supply chain. MediaTek, Foxconn Industrial Internet, Delta Electronics, Hon Hai, Unimicron, Quanta, AVC, Wiwynn, Lite-On, and many others are all being repriced by the current AI capital expenditure cycle.

This shows that the market is beginning to understand one critical point: AI is not only about GPUs, and it is not only about advanced process nodes.

AI needs foundry manufacturing. It needs CoWoS and advanced packaging. It needs high-end PCBs and substrates. It needs thermal modules, power management, server assembly, rack-scale system integration, and global logistics.

In the past, Taiwan was often simplified as a “contract manufacturing island.” But in the AI era, Taiwan is no longer just a manufacturing base. It has become the system-level manufacturing hub of global AI hardware infrastructure.

When NVIDIA wants to scale GPUs, CPUs, networking chips, switches, NVLink, HBM, and rack-scale platforms into global data centers, it inevitably returns to the Taiwan supply chain.

Why Jensen Huang Needs Taiwan

Jensen Huang’s visit to Taiwan was not only about emotional connection, nor was it merely a stage for saying “Taiwan is booming.” What he truly needs is the collaborative efficiency of Taiwan’s supply chain.

The biggest difference between AI servers and traditional servers is that AI servers are no longer simple combinations of motherboards and chassis. They are complex engineering systems involving power delivery, thermal management, signal integrity, packaging, memory, networking, and system-level integration.

GPU power consumption is rising. HBM bandwidth is expanding. Rack power density is increasing rapidly. Liquid cooling and power architecture are becoming part of platform competitiveness.

That is why this dinner brought together TSMC, OSAT players, thermal solution providers, power companies, ODMs, motherboard makers, server vendors, and industrial computer companies.

NVIDIA is not only selling chips. It is pushing an entire AI Factory architecture. This architecture requires Taiwan’s supply chain to compress design, trial production, volume production, delivery, and customer support into an extremely short cycle.

In the AI era, competition is no longer only about who has the most powerful chip. It is about who can most quickly turn the most powerful chip into a manufacturable, deliverable, serviceable, and scalable data center system.

Tung Tzu-hsien Pointed to the Real Issue: AI Is Also About Talent and Power

Pegatron Chairman Tung Tzu-hsien told the media that Taiwan is currently in the middle of the AI wave, and that AI is the central point of technological progress. He said Taiwan will play an important role.

He also noted that Taiwan needs to make a lot of effort to keep moving forward, including in talent development. Many companies are expanding capacity, and one of the most important issues is the pursuit of more stable and more sufficient power supply.

This statement goes straight to Taiwan’s two biggest bottlenecks in the AI supply chain: talent and energy.

• First, the AI hardware supply chain does not only need electrical engineers. It also needs talent in thermal engineering, mechanical design, power electronics, materials, packaging, optical communications, firmware, software, and system integration.

  AI servers are not a single-component industry. They are the sum of cross-disciplinary engineering. Taiwan’s long-term advantage in manufacturing and supply chain execution is now being amplified by AI demand, but the pressure on talent supply is also rising.

• Second, electricity is becoming the new ceiling for Taiwan’s technology sector.

  AI data centers, advanced process fabs, advanced packaging facilities, server manufacturing lines, and testing lines are all power-intensive. In the future, the core of global AI competition will not only be about how many tokens each GPU can generate. It will also be about whether the entire supply chain can secure enough stable energy and convert every kilowatt-hour into more computing output.

If Taiwan wants to remain at the center of the AI supply chain, power stability, green energy access, grid resilience, and high-power data center infrastructure will become national-level industrial issues.

ASRock Rack Shows the Real Constraint: Demand Is Strong, but Components Are Tight

ASRock’s subsidiary ASRock Rack focuses on AI server business. Its chairman Hsu Lung-lun recently said that end demand remains very strong, but second-quarter revenue will be somewhat constrained by tight NVIDIA and related component supply. As components gradually become available in the third quarter, shipments are expected to rebound significantly and drive second-half growth.

This is an important signal. It shows that the current AI server market is not facing a demand problem. The real constraint is still on the supply side.

The bottleneck may come from GPUs, networking chips, power modules, thermal components, PCBs, connectors, mechanical parts, or even rack-scale assembly and testing capacity.

ASRock Rack also noted that general-purpose server demand has exceeded expectations. The company expects general-purpose servers to account for more than 30% of total server revenue in the second quarter, up sharply from the previous estimate of about 20%. It also expects annual shipments of general-purpose servers to grow 50%.

This means AI demand is not simply replacing traditional servers. Instead, it is lifting the entire data center investment cycle. AI servers, CPU servers, storage, networking, and edge nodes are expanding together.

The market has focused too heavily on GPUs. But the real AI infrastructure cycle is the expansion of the entire data center hardware stack.

Jensen Huang’s Humor Reflects Deep Trust with Taiwan’s Supply Chain

There was also a lighter moment during the dinner. When Jensen Huang saw a portrait, he joked: “Is this really a painting of me? I guess it looks more like TSMC President C.C. Wei. The white hair makes it look more like C.C. than me. This painting could be me or it could be C.C.”

The room burst into laughter. C.C. Wei then walked over to take a photo with Jensen Huang and the portrait.

This looked like a casual moment, but it reflected the deep trust between NVIDIA and Taiwan’s supply chain.

For NVIDIA, TSMC is not just a foundry partner. It is the most important manufacturing foundation of the AI era. For Taiwan’s supply chain, NVIDIA is not just a customer. It is the platform company that has helped reprice the entire Taiwanese technology sector.

As global AI infrastructure enters a high-speed expansion phase, the relationship between NVIDIA and Taiwan is no longer just a chip procurement relationship. It has become a symbiotic relationship between a platform company and a system-level supply chain.

Taiwan Is Becoming the Physical Construction Team of the AI Factory

If the United States defines AI models, cloud platforms, and GPU architecture, Taiwan is the region that turns these architectures into mass-producible hardware.

TSMC manufactures the most advanced GPUs and ASICs. ASE, SPIL, and other OSAT companies handle packaging and testing. Unimicron, Kinsus, and other substrate and PCB suppliers provide advanced interconnect foundations. Delta Electronics and Lite-On support power and energy management. AVC, Auras, and thermal solution providers handle the power density problem. Quanta, Hon Hai, Wistron, Wiwynn, Inventec, Pegatron, and Compal turn chips into AI servers and rack-scale systems deliverable to cloud customers.

This is Taiwan’s real value.

It does not only make one component. It can integrate an entire AI hardware supply chain within the shortest cycle in the world.

In the AI Factory era, chips are only the starting point. The real battlefield is system-level delivery capability, and this is where Taiwan is strongest.

The Market Is Redefining What “Taiwan Tech” Means

In the past, the market often valued Taiwanese technology companies through the lens of gross margin, contract manufacturing, and cyclical demand.

After the rise of AI, that valuation logic is changing.

The value of the AI supply chain no longer comes only from manufacturing cost advantage. It comes from irreplaceable engineering coordination.

When NVIDIA, Amazon, Google, Microsoft, Meta, and other cloud giants need to rapidly expand AI data centers, they do not only need a single supplier. They need an entire supply chain network that can scale together.

This is why Taiwan’s technology market capitalization has expanded rapidly. The market is beginning to recognize that AI infrastructure is not a short-term theme. It is a long-cycle capital expenditure trend.

As long as AI models continue to grow, inference demand continues to expand, and data centers continue to scale, Taiwan’s supply chain will continue to benefit.

But the risks are also clear.

If AI capital expenditure slows, or if pressure from electricity, land, talent, and geopolitics increases, the high valuations of Taiwan’s AI supply chain will also face renewed scrutiny.

The Trillion-Dollar Dinner Is Not the End. It Is the Beginning of Taiwan’s Next Challenge

This dinner showed Taiwan’s technology sector at a high point. Jensen Huang sitting with Taiwan’s leading technology executives symbolized Taiwan’s importance in the AI era.

But the deeper question is whether Taiwan can turn this AI dividend into structural competitiveness for the next decade.

The answer depends on several issues.

• First, Taiwan must continue expanding advanced process and advanced packaging capacity, especially CoWoS, SoIC, HBM integration, and future 3.5D packaging capability.

• Second, Taiwan must solve system bottlenecks in thermal management, power delivery, optical communications, and high-end PCB materials, so that the AI server supply chain is not constrained by a single component.

• Third, Taiwan must solve its energy and talent problems. Without stable power, there is no AI Factory. Without cross-disciplinary engineering talent, there is no system-level innovation.

• Fourth, Taiwanese companies must move beyond manufacturing and participate more deeply in specification definition, system architecture, hardware-software integration, and global service capability.

In the future, the companies with real pricing power will not only be those that can manufacture. They will be those that can help define the platform.

Conclusion: Whoever Controls Taiwan Controls the Future of AI Hardware

Jensen Huang’s trillion-dollar dinner delivered a simple message: the AI revolution is not happening only in the cloud, and it is not happening only inside models. It is reshaping the global hardware supply chain.

Taiwan is standing at the most critical point of that chain.

From TSMC to Hon Hai, from Quanta to Wiwynn, from Delta Electronics to AVC, from Unimicron to SPIL, from ASUS, Gigabyte, and MSI to ASRock Rack, these companies together form the physical backbone of global AI infrastructure.

This dinner was not a victory party for Taiwan’s technology industry. It was the opening scene of the next stage of competition.

As AI moves from model competition to infrastructure competition, the key question is no longer only who has the strongest GPU. It is who can integrate GPUs, power, thermal management, packaging, memory, networking, and server systems into a manufacturable, deliverable, and scalable AI Factory.

That is why Taiwan is being repriced by the world.

Jensen Huang has once again placed Taiwan at the center of the global AI map. His message was direct: Taiwan is not merely participating in the AI revolution; Taiwan is one of its epicenters.

This statement should not be read only as a compliment. It is a strategic definition of Taiwan’s new role in the AI era. NVIDIA’s relationship with Taiwan is no longer just about chips, foundry services, or GPU assembly. It is about building the entire physical foundation of AI factories: silicon, advanced packaging, high-speed PCB, CCL materials, power delivery, thermal management, system integration, and data center infrastructure.

In other words, NVIDIA is not just buying components from Taiwan. NVIDIA is building the AI industrial stack with Taiwan.

From GPU Supply Chain to AI Factory Supply Chain

In the past, Taiwan’s semiconductor story was mainly centered on TSMC and advanced process technology. That story is still critical, but it is no longer sufficient.

The AI infrastructure cycle has expanded the boundary of value creation. A GPU is no longer just a chip. It is part of a rack-scale computing system. A rack is no longer just a server cabinet. It is becoming a high-density AI factory unit. As NVIDIA platforms move from GB200 and GB300 toward Rubin and Vera Rubin, the system boundary keeps expanding from chip to package, from package to board, from board to rack, and from rack to the entire data center power architecture.

This is why Taiwan matters so much. Taiwan is one of the few places in the world that can convert architecture into mass production at system scale.

NVIDIA’s Taiwan Spending Is a Signal of Structural Dependency

According to Jensen Huang, NVIDIA’s annual procurement and spending in Taiwan has grown dramatically from roughly US$10–15 billion several years ago to around US$100 billion, and may move toward US$150 billion in the future. This is not just a larger purchase order. It is a reflection of how AI hardware value is being redistributed across the supply chain.

NVIDIA’s demand is no longer limited to wafers, GPUs, or accelerator cards. The company now needs full AI system manufacturing capacity. That includes advanced packaging, server platforms, high-speed networking, power modules, liquid cooling, rack integration, and eventually AI data center deployment.

This is the real meaning behind “Taiwan is booming.” Taiwan is no longer only a semiconductor manufacturing center. It is becoming the operating system of global AI hardware production.

EMC and ITEQ: Why CCL Materials Are Becoming AI Infrastructure Assets

The recent updates from Taiwan’s CCL leaders are particularly important. Elite Material Co., commonly referred to as EMC, and ITEQ, are both seeing strong demand from AI servers, 800G and 1.6T switches, high-speed computing platforms, and cloud data center infrastructure.

This matters because copper-clad laminate is not a glamorous component. It is not as visible as GPU, HBM, or CoWoS. But in the AI infrastructure era, CCL is becoming a performance-critical material.

As data rates move from 112G to 224G SerDes, the board is no longer just a passive carrier. It becomes part of the signal path. Material loss, dielectric stability, copper roughness, dimensional control, thermal reliability, and process consistency all directly affect system performance.

For AI servers and high-speed switches, low-loss materials are not optional. They are part of the architecture.

Why “Full Capacity” at CCL Makers Is an Early Indicator

When EMC and ITEQ talk about strong demand visibility extending toward 2028, the market should pay attention. CCL suppliers sit upstream of PCB makers, ODMs, switch platform vendors, and system integrators. When material demand is locked in several years ahead, it often means the downstream platform roadmap is already being planned.

This is not a simple inventory restocking cycle. It is a platform migration cycle.

AI GPUs are becoming more powerful. HBM capacity is increasing. Switch bandwidth is moving to 800G and 1.6T. Rack power density is rising. PCB layer counts are increasing. Board sizes are becoming larger. Signal integrity requirements are becoming stricter.

All of these changes create structural demand for higher-end CCL materials.

The Real Bottleneck Is Moving from Compute to System Architecture

• The first wave of the AI boom was defined by GPU availability.

• The second wave is being defined by packaging capacity, especially CoWoS.

• The next wave will increasingly be defined by system-level constraints: power delivery, thermal management, high-speed signaling, and data center infrastructure.

This is where Taiwan’s ecosystem becomes strategically important.

Taiwan does not only manufacture chips. It manufactures the full AI system. The island has TSMC for leading-edge silicon, ASE and SPIL for advanced packaging, major server ODMs for system integration, PCB and CCL companies for high-speed boards, thermal solution suppliers for liquid cooling, and power electronics companies such as Delta Electronics for power infrastructure.

This density of industrial capability is extremely difficult to replicate.

NVIDIA’s 800V HVDC Roadmap Shows the Next Stage of AI Infrastructure

NVIDIA’s push toward 800V HVDC power architecture is one of the clearest signals that AI has entered a new phase. Traditional 54V rack power architectures were designed for kilowatt-scale systems. Future AI racks are moving toward hundreds of kilowatts and eventually megawatt-scale density.

This means AI infrastructure is no longer just a semiconductor problem. It is also an electrical infrastructure problem.

The industry now has to solve several problems simultaneously: how to deliver power efficiently into the rack, how to reduce conversion loss, how to minimize copper usage, how to manage heat, and how to keep the entire data center reliable under extreme power density.

This is why the AI supply chain is expanding from semiconductors into power semiconductors, power modules, busbars, liquid cooling, switchgear, and data center electrical systems.

AI workloads are growing exponentially, driving higher power demand in data centers. Traditional 54V in-rack power distribution was designed for kilowatt-scale racks and cannot support the megawatt-scale racks now entering modern AI factories.

Starting in 2027, NVIDIA is leading the transition toward 800V HVDC data center power infrastructure to support IT racks of 1MW and above. To accelerate adoption, NVIDIA is working with key partners across the data center electrical ecosystem, including:

• Chip suppliers: Infineon, MPS, Navitas, ROHM, STMicroelectronics, Texas Instruments

• Power system components: Delta, Flex Power, Lead Wealth, LiteOn, Megmeet

• Data center power systems: Eaton, Schneider Electric, Vertiv

This initiative is designed to drive innovation and build a more efficient and scalable power delivery architecture for the next generation of AI workloads, while improving reliability and reducing infrastructure complexity.

Taiwan’s Role: Turning NVIDIA’s Architecture into Manufacturable Reality

NVIDIA designs the architecture, but Taiwan helps make it manufacturable.

This is the key point. NVIDIA’s AI roadmap is not only a chip roadmap. It is a system roadmap. Every new generation requires tighter coordination across foundry, packaging, substrates, PCB, CCL, power, cooling, mechanical design, and rack assembly.

Taiwan’s advantage lies in this coordination capability. Its suppliers are geographically close, technically experienced, and deeply integrated into each other’s development cycles. This allows NVIDIA to move faster from design concept to production ramp.

For AI hardware, speed of iteration is a competitive weapon. Taiwan gives NVIDIA that speed.

EMC, ITEQ, and the Second-Layer Revaluation of the AI Supply Chain

The market has already revalued the first layer of the AI supply chain: GPU, HBM, CoWoS, and AI server ODMs. But the second layer is still being repriced.

This second layer includes high-end CCL, low-loss materials, high-speed PCB, connectors, power modules, liquid cooling, busbars, and data center electrical infrastructure.

EMC and ITEQ are important because they represent this second-layer revaluation. Their products sit inside the physical highways that allow AI systems to move data at high speed and high reliability. As AI systems become larger and faster, these materials become more strategic.

In the 800G, 1.6T, and 224G SerDes era, material quality directly affects system feasibility. A lower-loss laminate can reduce design complexity. Better dimensional stability can improve yield. More reliable materials can reduce system failure risk.

This is why CCL is no longer just a cost item. It is becoming a strategic AI infrastructure material.

Taiwan Is Becoming an AI Industrial Island

The phrase “Taiwan is the epicenter of AI” should be understood in industrial terms.

Taiwan is becoming an AI industrial island. Its role is not limited to semiconductor fabrication. It is becoming the place where AI chips are transformed into deployable AI factories.

This includes wafer manufacturing, advanced packaging, high-speed substrates, CCL, PCB, server motherboards, switch boards, accelerator boards, rack integration, cooling systems, and power infrastructure.

The AI era is therefore expanding Taiwan’s strategic importance. In the smartphone era, Taiwan manufactured key components and devices. In the AI era, Taiwan is manufacturing the infrastructure layer of machine intelligence.

SemiVision View: NVIDIA and Taiwan Are Building the Physical Layer of AI

The key message is simple: NVIDIA cannot scale AI without Taiwan, and Taiwan’s semiconductor ecosystem is being reshaped by NVIDIA’s AI roadmap.

The first stage of the AI boom was about compute. The second stage is about infrastructure. This shift will continue to reprice the entire Taiwan supply chain.

TSMC remains the core. CoWoS remains critical. But the next layer of value will come from materials, boards, power, cooling, and system integration. EMC and ITEQ are early examples of this transition.

AI users do not only need tokens. They need electricity. AI servers do not only need GPUs. They need high-speed materials, reliable power delivery, advanced cooling, and manufacturable system architecture.

That is why NVIDIA’s Taiwan story is not just about procurement. It is about industrial co-development.

Taiwan is no longer only the world’s semiconductor foundry base. It is becoming the manufacturing backbone of the global AI factory.

“Taiwan is booming!” NVIDIA CEO Jensen Huang repeatedly emphasized at the event.

He said he had been stressing Taiwan’s importance for many years and had long made clear that NVIDIA would continue increasing its investment in Taiwan. Around four to five years ago, NVIDIA’s annual spending in Taiwan was roughly US$10 billion to US$15 billion. Today, that figure has surged to around US$100 billion to US$150 billion.

“Now I have been proven right, haven’t I?” Huang said with satisfaction. “A single company investing US$150 billion will inject enormous momentum into Taiwan’s ecosystem.”

This was the first time NVIDIA publicly revealed the design and timeline for its new Taiwan headquarters, NVIDIA Constellation. The campus will cover 700,000 square feet and is expected to break ground by the end of 2026, with completion and move-in scheduled for 2030. Huang said NVIDIA currently has around 1,000 employees in Taiwan, and the new headquarters will be able to accommodate up to 4,000 employees once completed.

“We want to become the first company in the world to replicate the design of our headquarters buildings across different parts of the world,” Huang said. He explained that NVIDIA’s new Taiwan headquarters will share the same design concept as the company’s next-generation headquarters building in the United States. Both projects are designed by renowned Taiwanese architect Kris Yao, who has worked with NVIDIA for more than a decade and is also one of the key architects behind NVIDIA’s global headquarters.

NVIDIA Constellation reflects the company’s core culture of transparency and openness. The building will feature a fully transparent exterior and will be composed of triangular and polygonal geometric elements.

Interestingly, the building will not include any elevators. Huang said frankly that he does not like elevators because elevators mean “waiting” — waiting to go up, waiting to go down, and wasting too much time. In addition, all parking will be placed underneath the building, allowing the entire site to maximize open space above ground.

The campus will also include skybridges, and one of the skybridges will even feature a bar. Huang jokingly said that, according to NVIDIA’s company culture, the bar is the most important facility in the entire building.

NVIDIA also added that it took 18 months to secure the land for this project, and the company expressed special gratitude to Taipei Mayor Chiang Wan-an and the Taipei City Government team for their strong support.

NVIDIA Constellation: An Architectural Proposal for an Open AI Campus in Taipei

From an architectural perspective, the four images present NVIDIA Constellation not simply as a corporate office, but as a low-rise, transparent technology campus embedded within Taipei’s urban landscape.

The building placed along the riverside, with mountains, city blocks, and public infrastructure forming the background. Instead of creating a dominant high-rise tower, the proposal adopts a horizontal and open campus form. The building appears light, transparent, and visually permeable, suggesting a workplace that is meant to connect with its surroundings rather than isolate itself from the city.

The building footprint is organized through a polygonal geometry, with multiple internal zones, courtyards, office areas, meeting spaces, connector spaces, and service cores. This layout creates a sense of movement and circulation. It is not a rigid rectangular office block; it is a spatial network designed for interaction, collaboration, and flexibility.

A building height of approximately 35 to 45 meters, with around six above-ground levels and underground parking or service space below. The design keeps the building relatively low and broad, emphasizing horizontal connectivity. This is consistent with a campus-style headquarters model, where daily movement, visual connection, and open circulation are more important than vertical hierarchy.

NVIDIA Constellation sits beside the river and near existing urban landmarks, showing how the building may become part of the Beitou-Shilin Technology Park’s future skyline. The proposal also preserves generous setback areas and open space along the street, helping the project maintain a softer relationship with the surrounding public realm.

Overall, these four images suggest an architectural concept built around transparency, openness, geometry, and urban integration.

NVIDIA Constellation is presented as a new type of AI-era headquarters: not a sealed corporate tower, but a visible, accessible, and collaborative campus that reflects the company’s culture and Taiwan’s growing role in the global technology ecosystem.

The TSMC Global R&D Center, located in Baoshan, Hsinchu Science Park, was designed by renowned Taiwanese architect Kris Yao and his firm, Kris Yao | Artech.

The building was inaugurated in mid-2023. For this major technology hub, which can accommodate more than 7,000 R&D engineers, Kris Yao introduced a strong sense of human warmth and spatial ingenuity.

One key feature is its transparent interactive space. Instead of reinforcing the cold separation traditionally associated with cleanrooms and office areas, Yao designed the enclosed wafer transport tracks as glass corridors. This allows employees and executives moving through the bright central atrium and surrounding walkways to see one another’s activities, creating a stronger sense of shared purpose and collective R&D spirit.

The building also emphasizes natural lighting and ecological design. It meets green building standards and uses the atrium to bring in natural daylight, water features, and a more relaxed spatial atmosphere. Even the basement cafeteria is equipped with light wells, creating a more harmonious and human-centered working environment.

Kris Yao is highly regarded for his work in technology facility design. In addition to TSMC’s Global R&D Center, he has also been involved in the design of TSMC’s Arizona fab in the United States, its Nanjing fab, and the new NVIDIA headquarters in Beitou-Shilin Technology Park, known as NVIDIA Constellation.

The semiconductor industry is entering a new constraint in capacity expansion: power.

In the past, when the industry discussed advanced process technology, the core issues were yield, capacity, mask layers, equipment lead times, and capital expenditure. But in the AI era, another more fundamental bottleneck is emerging: electricity.

AI servers, HBM, advanced packaging, and high-end logic chips are driving a new global investment cycle in wafer fabs. The problem is that a fab does not expand simply because it has land, capital, and equipment. When the power demand of an advanced fab approaches that of a small city, and when EUV, etching, deposition, metrology, cleanrooms, and utility systems are all added together, energy is no longer just an operating cost. It becomes a precondition for capacity expansion.

This is why ASML’s recent sustainability briefing in Taiwan may appear to be about ESG and energy saving, but its deeper significance is tied to the systemic bottlenecks of advanced process expansion.

Grace Wang, General Manager of ASML Taiwan, stated that semiconductors are a critical foundation for digitalization and AI development, which means the industry must assume greater responsibility in energy and sustainability. ASML will continue to support the long-term development of the semiconductor industry through technology innovation, manufacturing efficiency improvements, and close collaboration with customers and supply chain partners.

The key word here is not only “sustainability,” but “technology innovation.”

For wafer fabs, meaningful energy saving does not come merely from using less air conditioning in offices or sourcing more renewable power for buildings. The real issue is whether the most critical process equipment can produce more wafers under the same power conditions.

ASML’s numbers are important: EUV energy consumption per wafer is expected to fall from 12.8 kWh in 2018, during the NXE:3400 era, to 2.8 kWh by 2031 with the NXE:4600. In other words, the EUV energy consumed per wafer will be reduced to around 22% of the 2018 level — almost one-fifth.

This is not simply about making the machine “more power efficient.” It is about redesigning the efficiency logic of the entire lithography system.

The Real Issue Is Not How Much Less Power the Tool Uses, but How Many Wafers It Can Produce with the Same Power Budget

To understand ASML’s EUV energy roadmap, one cannot look only at the total power consumption of the machine. Two indicators must be examined together: Absolute Power, meaning the tool’s power consumption as a percentage of the 2018 baseline, and Energy per Wafer, meaning how much energy is allocated to each wafer.

These two numbers do not move in exactly the same direction. That difference is the key to the entire roadmap.

The NXE:3400 in 2018 serves as the baseline. At that time, the tool’s absolute power was set at 100%, energy consumption per wafer was 12.8 kWh, and throughput was around 112 wafers per hour. By 2031, with the NXE:4600, ASML expects absolute power to decline to 77%. In other words, the total power consumption of the tool itself will fall by only about 23%. If we look only at this number, the improvement may not appear dramatic.

But during the same period, energy per wafer falls from 12.8 kWh to 2.8 kWh. The reason is that NXE:4600 can process around 400 wafers per hour, nearly 3.6 times the 2018 level.

This means ASML is not simply turning EUV into a “low-power machine.” It is enabling one machine to process far more wafers within a similar power budget. For wafer fabs, this has far greater strategic significance than simply reducing the rated power of a tool.

When fabs plan capacity expansion, power applications are usually based on the combined load of equipment, facilities, and utility systems. But the real manufacturing economics depend on how much power cost is allocated to each wafer. When the same EUV tool can process more wafers per hour, electricity consumption no longer rises in direct proportion to wafer output. This creates new flexibility in capacity expansion.

This is also why High-NA EUV tools can still reduce energy per wafer even though they are physically larger, more complex, and consume more power. The NXE:4200G and NXE:4200H have absolute power ratios of 94% and 96%, respectively, almost returning to the 2018 power level. But because their throughput rises to around 300 and 330 wafers per hour, their energy consumption per wafer can still be reduced to roughly one-third of the 2018 level.

In other words, against the backdrop of AI-driven demand for advanced process capacity, the key energy-saving question for EUV is not “how much less electricity does one tool consume?” but “how many wafers can one kilowatt-hour expose?”

Below we will share:

• Sleep Mode: Stopping EUV from Burning Power When It Is Not Actually Working

• Hydrogen Recycling and 32°C Cooling Water

• The Real Energy Value of High-NA EUV Is Not That Each Tool Uses Less Power, but That the Whole Fab Runs Fewer Multiple-Patterning Steps

• Taiwan’s Role: EUV Energy Reduction Is Not a European Sustainability Topic, but a Real Constraint in Taiwan’s Advanced Process Expansion

• EUV Energy Reduction Will Reshape the Cost Structure of the AI Chip Supply Chain

Read more

In Taiwan’s semiconductor map, TSMC is usually understood as the global leader in advanced process technology, while Vanguard International Semiconductor Corporation, or VIS, is often categorized as a mature-node foundry. This classification is directionally correct, but it is not sufficient.

VIS is not simply a smaller version of TSMC. Nor is it merely another 8-inch wafer foundry competing in the low-growth mature-node market. Its strategic position is much more specific: VIS is a long-standing TSMC-affiliated company, an independent foundry, and a key platform for preserving and monetizing mature-node value within Taiwan’s semiconductor ecosystem.

The relationship between TSMC and VIS cannot be explained by the simple language of parent and subsidiary. Legally and operationally, VIS is not a TSMC subsidiary. TSMC has long been its largest single shareholder, with a stake around the high-20% range, but it does not hold majority control. VIS is independently listed, has its own board, its own management team, and its own capital allocation discipline.

However, it would also be inaccurate to describe VIS as just another unrelated foundry. Its history, technology roots, customer trust, and strategic role are closely tied to TSMC. The better way to understand VIS is this: it is TSMC’s non-subsidiary ally in mature and specialty processes. It sits outside TSMC’s direct operating structure, but inside the broader strategic logic of Taiwan’s semiconductor division of labor.

This distinction matters. As TSMC moves deeper into 3nm, 2nm, A16, CoWoS, SoIC, and next-generation AI infrastructure, it must continuously reallocate capital, talent, cleanroom space, and management attention toward the highest-value frontier. But the semiconductor world does not run only on advanced logic. Power management ICs, display drivers, MOSFETs, IGBTs, analog ICs, mixed-signal devices, MEMS, sensors, protection devices, and interposer-related processes remain essential to every system.

That is where VIS becomes strategically important.

TSMC defines the height of Taiwan’s semiconductor industry. VIS helps support its thickness.

From DRAM Policy Mission to Mature-Node Foundry Platform

To understand VIS properly, we need to go back to Taiwan’s semiconductor industrial history in the 1990s.

At that time, Taiwan had already built strong capabilities in PC manufacturing and electronics assembly, but key memory components were still heavily dependent on imports. To address this weakness, Taiwan’s Industrial Technology Research Institute promoted the Submicron Project, which aimed to build domestic capabilities in advanced manufacturing technology. VIS was established in 1994 under this broader industrial policy framework.

In its early years, VIS was closely associated with Taiwan’s DRAM ambition. TSMC was one of its major founding shareholders, and Morris Chang played an important role in its early development. The company’s original mission was not to become a specialty foundry, but to help Taiwan enter the DRAM manufacturing field.

But DRAM quickly became one of the most brutal markets in semiconductors. By the late 1990s, global DRAM pricing collapsed, and the industry turned into a capital-intensive battlefield dominated by players with massive scale and aggressive cost structures. For VIS, continuing to compete in standard DRAM would have meant entering a red ocean against larger memory giants from Korea, Japan, and the United States.

The decisive turning point came around 2000, when VIS exited standard DRAM and transformed itself into a foundry business focused on 8-inch specialty processes. This decision did not just save the company; it reshaped its identity. VIS moved away from being a policy-driven DRAM company and became a critical mature-node foundry platform inside Taiwan’s semiconductor ecosystem.

This historical pivot explains why VIS should not be viewed as a low-end foundry. It was born from Taiwan’s effort to internalize semiconductor technology, but it survived by finding a more sustainable position: specialty process manufacturing, where long product cycles, customer-specific process tuning, high-voltage capability, and manufacturing reliability matter more than transistor scaling.

VIS Is Not TSMC’s Subsidiary, but It Is Not an Ordinary Peer Either

One of the most common market misunderstandings is whether VIS is a TSMC subsidiary. The answer is no.

TSMC has long been the largest single shareholder of VIS, but it does not own more than 50% of the company. VIS has independent corporate governance, independent management, and its own capital market identity. This independence is not just a legal detail; it is strategically necessary.

In the foundry business, customer trust is everything. Customers care deeply about data confidentiality, process know-how, product roadmaps, and competitive neutrality. If VIS were viewed as a directly controlled subsidiary of TSMC, some customers might worry about information boundaries and conflict of interest. By maintaining operational independence, VIS can serve customers as a neutral specialty foundry while still benefiting from historical technology roots and strategic trust with TSMC.

This creates a unique structure. VIS is not controlled by TSMC, but it is not disconnected from TSMC either. It has historical ties, technology lineage, and strategic complementarity. In semiconductor terms, this is not a parent-subsidiary relationship. It is a division-of-labor relationship.

TSMC focuses on the most capital-intensive frontier: advanced logic, advanced packaging, AI accelerators, HPC chips, and high-end mobile SoCs. VIS focuses on processes where maturity, reliability, voltage handling, customization, and cost stability matter more than leading-edge scaling.

This is why VIS should not be called a “small TSMC.” It is a different type of asset. TSMC is a technology ceiling company. VIS is a mature-process value-floor company.

Below we will share:

• The Semiconductor Industry Does Not Only Move Toward Smaller Nodes

• AI Demand Is Changing VIS’s Revenue Logic

• PMIC: The Hidden Power Architecture Behind AI and High-Performance Electronics

• 8-inch Capacity: Less About Total Volume, More About Value Mix

• VSMC: From a 12-inch PMIC Expansion to an AI-Relevant Specialty Process Platform

• VIS Continues to Focus on Specialty Mature Processes, While Leaving the Door Open for 22nm

• Taiwan’s Semiconductor Strength Is Not Just One Company, but Layered Specialization

• TSMC recently announced two major divestment plans related to its subsidiary, Vanguard International Semiconductor (VIS)

Read more

CPO (Co-Packaged Optics) is heating up fast and becoming one of the hottest topics in the semiconductor and AI industry right now.

Driven by the explosive demand for massive bandwidth and ultra-low power in next-generation AI factories, SiPh/CPO has emerged as the critical enabling technology for both today’s scale-out networking and tomorrow’s scale-up xPU fabrics. Major players are moving quickly: Intel is pushing Optical Compute Interconnect (OCI), NVIDIA has unveiled its Quantum-X and Spectrum-X Photonics platforms, TSMC, GlobalFoundries, Broadcom, Marvell, and Ayar Labs are all rolling out new products and manufacturing platforms. The market momentum is unmistakable — CPO is no longer just a promising concept, but a rapidly commercializing solution that the entire industry is racing to adopt.

The Critical Shift from Electrons to Photons: How CPO Test Interfaces Are Becoming a New Battleground for AI Infrastructure

AI infrastructure is entering a critical inflection point. In the past, when the semiconductor industry discussed computing power, the focus was mostly on GPUs, ASICs, HBM, advanced process nodes, and advanced packaging. Today, however, the real bottleneck limiting system performance is gradually shifting from “whether chips can compute” to “whether data can move efficiently.”

This is why CPO, or Co-Packaged Optics, has become one of the most closely watched technologies in the industry. CPO is not merely about making optical modules smaller, nor is it simply about increasing transmission speed by one generation. More importantly, it represents a new stage in AI system architecture, where traditional electrical interconnects are gradually moving toward deeper optoelectronic integration.

From WinWay’s CPO technology forum, it is clear that the challenges of CPO do not lie only in optical engines, silicon photonics chips, or packaging integration. They also lie in mass-production testing. When optics, electrical signals, thermal management, mechanical alignment, and high-speed signaling all converge within the same package, the test interface is no longer just a supporting role in the semiconductor manufacturing process. It becomes a critical factor determining whether CPO can truly move into commercial deployment and volume production.

The Real Bottleneck in the AI Era Is Not Only Computing Power, but Data Movement

The core challenge of AI servers is shifting from single-chip performance competition to system-level competition in bandwidth, latency, and power consumption.

In large model training and inference, GPUs or ASICs do not operate in isolation. They must continuously exchange massive amounts of data with HBM, switches, NICs, optical modules, and the broader data center network. As model size, parameter count, and token traffic continue to grow, data movement itself becomes a major cost.

Traditional copper wires or PCB traces face clear limitations under high-speed transmission. When signal speeds move into the 112 Gbps, 224 Gbps, and eventually 448 Gbps range, electrical signals transmitted through copper face three major challenges: higher loss, higher power consumption, and shorter transmission distance.

This is not a problem that can be fully solved simply by switching to better materials. It is a sign that physical limits are approaching. High-speed electrical signals in copper are affected by skin effect, dielectric loss, reflection, crosstalk, and package parasitics. The higher the speed, the shorter the viable transmission path, the tighter the design tolerance, and the higher the overall system cost.

Therefore, what AI infrastructure needs is not only faster chips, but also more efficient data channels. This is where optical communication creates value. Optical signals offer low loss, long-distance transmission, high bandwidth, and immunity to electromagnetic interference. They can redefine how chips, switches, and networks are connected inside the data center.

Below we will share:

• The Core Meaning of CPO: Bringing Optical Engines Closer to Computing Chips

• The Hardest Part of CPO Is That It Pushes Testing to the Physical Limit

• WinWay’s Role: From Electrical Test Interfaces to CPO Optoelectronic Integration Test Platforms

• HyperSocket: A Test Interface Upgrade for Large Packages and High Pin Counts

• Thermal Management Is Becoming a Core Battleground for Test Interfaces

• Before CPO Reaches Volume Production, CPC May Serve as a Transitional Solution

• Glass Substrates and Standardization Will Determine the Speed of CPO Scaling

• AI Chip Shipments Drive Demand for Testers

• Global Semiconductor Test Consumables Vendors Are Entering a Volume-and-Value Growth Cycle

Read more

In recent political debate, the claim that “Taiwan stole America’s semiconductor technology” has once again been amplified. It is a simple sentence, emotionally powerful and politically useful. But from the perspective of industrial history, technology tran…

Read more

From Node Scaling to System Scaling: Why Semiconductor Process Technology Is Becoming Application-Driven

For decades, the semiconductor industry was defined by one dominant question: who could move to the next process node first? From 90nm to 28nm, from 7nm to 5nm, and now toward 3nm and 2nm, the industry’s competitive logic appeared straightforward: smaller geometry meant higher density, lower power, better performance, and stronger pricing power.

But that logic is no longer sufficient.

The next phase of semiconductor competition is not simply about shrinking transistors. It is about matching the right process, the right packaging architecture, the right reliability standard, and the right power-performance profile to the right application. Smartphones, AR glasses, electric vehicles, autonomous driving systems, and robots are no longer asking for the same type of chip. Each application has its own physics, cost structure, thermal envelope, safety requirement, and system architecture. This is why the industry is moving from node-centric scaling to application-driven system scaling.

The End of the One-Node-Fits-All Era

Advanced nodes remain critical. N5, N4, N3, and the coming N2 generation continue to define the cutting edge for mobile SoCs, AI accelerators, and high-performance computing. These nodes deliver higher transistor density, better energy efficiency, and stronger performance per watt. For smartphones and AI devices, that still matters enormously.

However, not every function benefits equally from the newest node. A mobile SoC may need a 3nm CPU or NPU, but its RF subsystem, image signal processor, power management IC, display driver, embedded memory, and sensor interface may be better served by mature or specialty processes. In automobiles, the central ADAS processor may migrate to 5nm, 3nm, or eventually 2nm, but microcontrollers, radar chips, CIS sensors, power devices, and battery management ICs will remain distributed across 28nm, 22nm, 16nm, BCD, RF, CIS, SiC, and GaN platforms.

This is the key structural shift: the future semiconductor platform is no longer a single monolithic node, but a heterogeneous system assembled from multiple process technologies.

Smartphones: The Original Driver of Advanced Logic Scaling

The smartphone remains one of the most demanding semiconductor platforms in the world. A modern mobile SoC integrates CPU cores, GPU blocks, ISP engines, 5G modems, Wi-Fi connectivity, DSPs, NPUs, memory controllers, security modules, and power management interfaces into a highly constrained thermal and battery envelope.

This is why mobile chips have historically been among the earliest adopters of advanced foundry nodes. The move from 7nm to 5nm, and then to 3nm, gave smartphone chip designers more transistors within the same die area while reducing energy consumption. For mobile devices, every milliwatt saved can become longer battery life, better sustained performance, thinner form factors, or more room for AI inference.

But even in smartphones, the industry is moving away from a purely monolithic model. Advanced logic may sit on N3 or N2, while RF, analog, image processing, memory, and connectivity blocks may be manufactured on different optimized nodes. Over time, packaging technologies such as InFO, 3D integration, and chiplet-based architectures will allow smartphone platforms to become more modular.

The implication is clear: future mobile performance will not come only from a smaller transistor. It will come from process partitioning, advanced packaging, memory proximity, thermal design, and system-level power management.

AR Glasses: Why Display Drivers Are Becoming Semiconductor Strategy

AR and VR devices introduce a different challenge. Unlike smartphones, near-eye displays must operate under extreme size, weight, heat, and power constraints. The display subsystem cannot simply consume more power, because heat is directly perceived by the user. It cannot occupy large board area, because the device must fit into glasses. It cannot tolerate slow response, because latency affects user comfort.

This is why high-voltage display driver technology is becoming strategically important.

TSMC’s N16HV process is an important signal. By introducing high-voltage capability into a FinFET platform, the display driver can become smaller, more power-efficient, and more suitable for OLED and near-eye display systems. According to the source material, N16HV offers higher gate density and lower power compared with N28HV, while also reducing chip area and power consumption for near-eye display applications.

This is not just an incremental display driver improvement. It suggests that AR glasses may require a new class of semiconductor platform: one that combines display driving, sensing, wireless communication, edge AI, and power management in a form factor closer to consumer electronics than traditional computing.

In other words, smart glasses will not be won by optics alone. They will be won by the semiconductor companies that can solve display power, sensor fusion, edge inference, thermal control, and miniaturized packaging at the same time.

Automotive: Advanced Nodes Meet Long-Lifecycle Reliability

Automotive semiconductors follow a different logic from consumer devices. A smartphone chip may be replaced every two to three years. A car platform may need to operate for more than a decade. This means automotive chips must satisfy long product lifecycles, wide temperature ranges, functional safety requirements, and strict reliability standards such as AEC-Q100.

At the same time, electric vehicles and autonomous driving systems are pushing automotive chips toward much higher compute intensity. ADAS and autonomous driving require real-time perception, sensor fusion, AI inference, and centralized decision-making. This is why the automotive architecture is moving from many distributed ECUs toward central compute and zonal control.

TSMC’s N2A automotive process reflects this direction. Based on the source text, N2A applies nanosheet transistor technology to automotive applications and is expected to support higher performance at the same power level versus N3A, with AEC-Q100 qualification targeted around 2028.

The deeper message is that automotive semiconductors are no longer only about mature nodes. They are splitting into two layers.

The first layer is the high-performance compute layer: ADAS SoCs, autonomous driving processors, AI accelerators, and centralized vehicle computers. These will increasingly adopt advanced nodes such as N5A, N3A, and eventually N2A.

The second layer is the control, sensing, power, and reliability layer: MCUs, radar, CIS, battery management, gate drivers, power ICs, and SiC/GaN modules. These will remain on specialized and mature process platforms.

The car of the future is therefore not a single semiconductor market. It is a multi-process, multi-package, safety-certified computing system on wheels.

Robotics and Physical AI: The Next Edge Computing Platform

Robotics may become one of the most important semiconductor growth vectors after smartphones and EVs. Unlike cloud AI, robotics requires intelligence to be embedded inside a physical machine. The robot must see, listen, feel, infer, decide, move, and correct itself in real time.

This is why the concept of Physical AI matters. A robot is not merely an AI model with motors attached. It is a closed-loop control system that must integrate sensors, actuators, edge processors, motor controllers, wireless links, power devices, safety mechanisms, and real-time software.

The source material emphasizes that next-generation robots require local AI processing, low-latency deterministic control, sensor fusion, and reliable communication between sensors, actuators, and central compute units.

This creates a very different semiconductor demand profile from traditional industrial automation. A humanoid robot or service robot may need:

CPU and NPU cores for AI inference; vision processors for cameras and depth sensors; radar or LiDAR interfaces for navigation; MCUs for motion control; power devices for actuators; wireless modules for connectivity; and secure processors for safety and identity.

The robot is therefore a semiconductor system that combines the characteristics of a smartphone, an electric vehicle, an industrial controller, and an AI edge server. This is why robotics will likely accelerate demand for heterogeneous integration rather than a single dominant node.

FinFET to GAA: The Transistor Is Still Important, But It Is No Longer Alone

The transition from FinFET to Gate-All-Around nanosheet transistors remains one of the most important technology shifts in advanced logic. FinFET improved electrostatic control by wrapping the gate around three sides of the fin. But as scaling moves below 3nm, variability, leakage, and drive current optimization become more difficult.

GAA nanosheet transistors improve gate control by surrounding the channel more completely. They also allow transistor drive current to be tuned by adjusting nanosheet width, giving designers more flexibility in balancing performance and power.

For high-performance computing, AI, and premium mobile SoCs, this transition is critical. But the transistor is no longer the only bottleneck. Power delivery, interconnect resistance, thermal density, memory bandwidth, packaging warpage, and signal integrity are becoming equally important.

That is why backside power delivery is emerging as another important scaling technology. By moving power delivery to the backside of the wafer, chip designers can reduce IR drop, free up front-side routing resources, and improve power efficiency in highly dense logic designs.

The conclusion is not that transistor scaling is ending. The conclusion is more precise: transistor scaling is becoming one component of system scaling.

Advanced Packaging: The New Scaling Layer

As the cost and complexity of advanced nodes rise, advanced packaging becomes the bridge between process technology and system architecture. CoWoS, InFO, chip-on-wafer, 2.5D integration, 3D stacking, hybrid bonding, and chiplet architectures allow designers to combine multiple dies fabricated on different process nodes.

This is especially important because different functions have different optimal nodes. Logic may require N2 or N3. SRAM may scale differently. Analog and RF may not benefit from the newest node. Power devices may require entirely different materials. Sensors may need specialized process modules.

Advanced packaging allows the industry to avoid forcing all functions onto one expensive monolithic die. Instead, it enables a more efficient partitioning of the system.

This is why advanced packaging is no longer a back-end manufacturing service. It is becoming a front-line architecture platform. The companies that control heterogeneous integration will increasingly shape the performance, cost, and scalability of future AI, automotive, AR, and robotics systems.

The Cost Wall: Why Specialty Processes Matter More

The economics of advanced nodes are becoming more severe. A leading-edge 3nm chip can require enormous design investment, complex IP qualification, expensive EDA flows, longer validation cycles, and higher mask costs. Not every application can absorb this cost.

This is why specialty processes are becoming more valuable. High-voltage FinFET for display drivers, embedded MRAM or FeRAM for edge devices, BCD for power management, RF-SOI for wireless, CIS processes for image sensors, SiC and GaN for power electronics, and automotive-qualified logic platforms all represent different forms of process differentiation.

The future is not simply “more advanced” or “more mature.” The future is more specialized.

For foundries, this means that process leadership will be measured not only by the smallest node, but also by the breadth of platforms they can offer. For chip designers, it means the key question is no longer “Which node is the most advanced?” but “Which combination of nodes and packages creates the best system?”

Strategic Outlook: The Semiconductor Industry Is Becoming a System Industry

The next decade of semiconductor competition will be shaped by four structural forces.

• First, advanced logic will remain essential for AI, mobile, and high-performance computing. N3, N2, and future nanosheet/CFET architectures will continue to define the performance frontier.

• Second, specialty processes will expand because every application has different physical constraints. AR needs low-power high-voltage display drivers. EVs need automotive-grade reliability and power semiconductors. Robots need real-time edge AI and deterministic control. Sensors need photonic, RF, MEMS, or imaging-specific platforms.

• Third, advanced packaging will become the true system integration layer. Chiplets, 2.5D, 3D stacking, and heterogeneous integration will allow the industry to combine advanced and mature nodes inside one optimized system.

• Fourth, cost and reliability will become as important as density. The best semiconductor solution will not always be the smallest node. It will be the architecture that delivers the right balance of performance, power, area, cost, reliability, and manufacturability.

Conclusion: The Real Race Is No Longer Nanometers, But System Fit

The semiconductor industry is entering a new phase. The old race was about shrinking the transistor. The new race is about matching process technology to system architecture.

Smartphones will continue to push advanced logic. AR glasses will force display drivers and sensor modules into ultra-low-power form factors. Electric vehicles will demand both leading-edge compute and long-lifecycle reliability. Robots will require the fusion of AI inference, sensing, motion control, and power electronics at the edge.

This is why the most important question for the next decade is not simply who reaches 2nm or 1.4nm first. The more strategic question is:

Who can build the most complete semiconductor platform for each application?

The winners will not be defined only by transistor density. They will be defined by their ability to integrate logic, memory, power, sensing, packaging, software, and reliability into one system-level solution.

That is the real meaning of the next semiconductor era: from process scaling to system scaling, from node competition to platform competition, and from silicon manufacturing to application-defined architecture.

Below we will share:

• 3D-Stacked SRAM and Near-Field Wireless Interconnect: A New Memory Bottleneck Solution for AI Inference Chips

• 3D-Stacked SRAM: Better Suited for Low-Latency AI Inference Than DRAM

• The Key Challenge Is Interconnect: TSV Is Not the Only Possible Answer

• From Multi-Drop to Multi-Hop: The Battle for Memory Bandwidth Density

• Fujitsu MONAKA: A 3D-Stacked SRAM CPU Architecture Built for the Next Era of AI and HPC

• Why MONAKA Moves Away from HBM

Read more

When HBM Becomes “Luxury Real Estate for Compute” How to Rebuild AI Memory Architecture

In today’s AI compute race, the spotlight seems fixed on GPUs vs. TPUs, model size, and inference speed — an arms race measured in TOPS, parameters, and latency. But if we zoom out, the real choke point in the industry is not algorithms or silicon design.

It is the physics and supply chain structure of memory.

Driven by the success of NVIDIA’s system-level architecture, HBM (High Bandwidth Memory) has effectively become the default memory configuration for high-end AI accelerators. In today’s AI infrastructure, memory is no longer a secondary component — it is a performance-defining element.

You can think of HBM as the most premium real estate in a megacity. The location is unbeatable: it sits extremely close to the compute die, connected through an interposer with thousands of ultra-wide data paths. The infrastructure is top-tier: 3D die stacking, TSV vertical interconnects, and advanced packaging technologies such as CoWoS enable unprecedented bandwidth density.

But premium real estate comes with structural consequences.

Prices are astronomical because manufacturing HBM is not just a matter of producing DRAM wafers. It involves:

• High-yield TSV formation

• Wafer thinning and precise stacking

• Thermal management for multi-die stacks

• Interposer-based advanced packaging

• CXL (Compute Express Link): Making Memory Coherent

Each step narrows the list of capable suppliers. As a result, only a handful of companies control meaningful HBM capacity. Supply expansion is slow, capital intensive, and yield-sensitive. In practical terms, this means:

Whether vendors want to sell, how much capacity they allocate, and to whom — is not entirely in the hands of the AI chip designer.

This dynamic transforms memory from a technical specification into a strategic dependency.

Below we will share:

• Why HBM Turned Into a Strategic Bottleneck

• The Core Idea: Decoupling Memory from the Compute Die

• Why “Closer is Better” Is Breaking Down

• Google’s Architectural Reframe

• OCS (Optical Circuit Switching): Memory on Demand

Read more

The TSMC 2026 Technology symposium sends a very clear message: the semiconductor industry is no longer entering a normal technology cycle. It is entering a new system architecture cycle driven by artificial intelligence. AI i…

Read more