• What are tested in CPO testing

• Three types of probes in CPO testing, their prices and main vendors

• Testing instruments, their prices and main vendors

• Key components/ modules of a testing station

• How CPO testing differs from EML optical module testing

• CPO coupling methods and their implication on testing

• Why testing is a major bottleneck for CPO production

• Two main competing products/ solutions in CPO testing

Covered companies include: ficonTEC/ RoboTechnik (300757.CH), FormFactor ($FORM), Advantest (6857.JP), Teradyne ($TER), Keysight ($KEYS), R&S ($RSGN), Semight (688808.CH), Focuslight (688167.CH).

Disclaimer: This publication is for informational and analytical purposes only. The views expressed here reflect my personal research and opinions at the time of writing and should not be construed as investment advice, a recommendation to buy or sell any security, or a solicitation to engage in any investment activity. I may hold positions in some of the companies or securities discussed, and my views may change without notice. Readers should conduct their own research and consult a qualified financial adviser before making any investment decisions. Investing involves risk, including the potential loss of principal.

Part 1: PIC Testing

In CPO testing, both electrical and optical signals need to be tested. Around 80% of the test parameters are electrical, but 80% of the complexity lies in optical testing. Therefore, PIC testing is a core part of the overall process.

Part 1.1 Three types of signals

In general, PIC testing covers three types of signals:

Electrical signal testing: A PIC contains components like modulators and photodetectors (PD) that are driven by electrical currents. Thus, electrical signals need to be tested for these components - for example modulators are tested for things like L-I-V curve, threshold current, and voltage to ensure the electrical-to-optical conversion works properly; and PDs are tested for dark current and photocurrent after being applied bias voltage.

High frequency testing: High-frequency RF signals after modulation are tested to ensure the module can handle high-bandwidth workloads as the light is encoded with data. The testing results include things like eye diagrams, bit error rate, and signal jitter. It is the more complex testing category but also the high-value one. Essentially, it tests how “good” the output signals look before they are sent into fiber networks.

Optical signal testing: Optical signals pass through passive components in the PIC, such as waveguides, switches, and attenuators. During the process, the signals will experience losses (return loss and insertion loss, for example). Therefore, parameters such as optical power and wavelength must be tested to ensure the signals maintain a certain quality level after the whole transmission process.

Part 1.2 Probes

In order to complete the testing, probes are used to send signals to and receive signals from the PICs. Corresponding to the three types of signals, there are three types of probes:

Electrical probes: are quite standard components, as they are also widely used in semiconductor testing - as a result, the technology is very mature. In PIC testing, they are used to provide power to optical components such as modulators, PDs, and lasers, as well as to retrieve electrical signals from the PICs for analysis.

Electronic probes are not expensive - usually, a few thousand dollars is enough for the entire testing station. At that cost, one electrical probe can typically support 500K to 1 million test cycles. However, in CPO testing, its lifespan can be reduced to ~250K cycles as it needs to transmit higher-current signals and faces stricter requirements for cleanliness and wear.

As for suppliers, FormFactor ($FORM) is the premium, industry-benchmark producer, while Chinese companies such as Semight (688808.CH) are gaining market share. The latter’s product quality is good enough for most testing scenarios while offering more competitive prices.

RF probes: are technically a type of electrical probes, but they are used specifically for high-frequency RF signals in testing - they inject or capture high-frequency RF signals from the PIC. These are high-priced products, typically selling for $100K+ per probe. Companies such as FormFactor ($FORM) and R&S ($RSGN) are the main providers.

Optical probes are used for optical signal testing. In terms of physical forms, the probes are typically two fibers coupled very close to the PIC - one for input and one for output. The fibers tips are embedded with microlenses, which are made mainly using two approaches: 3D-printed polymers and polished microlenses. The former is cheaper but more fragile, while the latter is more robust but more expensive. A key company for making the polished microlens is Focuslight (688167.CH).

These microstructures are designed to converge light into fibers for later transmission. They need to be positioned at an extremely precise and close distance from the PICs to minimize optical losses. This process takes a long time and requires high-end, premium, machines, which we will cover in later sections.

One 3D-printed optical probe is sold for around $3,000, while microlens-based probes are sold at higher prices. Major probe providers include FormFactor ($FORM), Technoprobe ($TPRO), Tokyo Electron (8035.JP), and MPI (6223.TW). FORM and TPRO appear to be more advanced than others in CPO optical probe development race.

Part 1.3 Testing instruments

Testing instruments are used to analyze signals captured by electrical and optical probes. For optical modules, the most commonly used instruments are oscilloscopes and Bit Error Rate Testers (BERTs). Oscilloscopes receive and test module’s output signals, typically displayed as eye diagrams, while BERTs are used to send signals and test the performance of the modules’ receiving subassembly capabilities.

Instrument requirement is closely tied to the lane bandwidth it can support. For example, an instrument capable of testing 200G-per-lane signals can sell for more than twice the price of one that supports only up to 100G per lane.

Between the two most common instruments, oscilloscopes are more complex and command much higher prices - For example, BERTs used on production lines may cost around $20K, while oscilloscopes can cost around $200K.

For oscilloscopes, Keysight ($KEYS) is the main vendor in the market, with dominant share in both R&D and production spaces. For BERTs, Keysight remains dominant in the R&D space, where requirements for instrument capability are higher but volume demand is lower, while Chinese firm Semight can now offer good-enough alternatives and is gaining share in the production-line space.

Companies like Keysight also sell testing solutions. For example, Keysight sells its end-to-end silicon photonics testing solutions exclusively to FormFactor, which leverages its probe expertise to build the final integrated solution.

Part 1.4 Testing station

Combine the testing probes and instruments, and you have the testing station. A testing station consists of three parts: the probe module, coupling module, and testing module. The probe module provides electrical and optical probes that send signals to and retrieve signals from the PICs. The coupling module aligns the optical probes with the PICs at micron-level precision; and the testing module consists of instruments that measure and analyze the signals retrieved from the PICs. Different instruments are required for different types of electrical, RF, and optical signals.

The coupling module is the most complex and currently least mature part of the system. It must achieve extremely high positioning accuracy of probes relative to the PICs, maintaining a 5-10um distance without touching the chip. Coupling is also one of the most time consuming parts of the process, taking around half a minute to complete alignment of just one optical channel. As a result, the coupling module is currently the main production bottleneck in testing.

A major player in the coupling space is ficonTEC, which is known for its highly sophisticated active coupling machines for optical testing. ficonTEC is owned by the Chinese public company RoboTechnik (300757.CH).

A testing station solution currently sells for around $1-1.5 million in the market (without the expensive RF probes and test instruments).

Part 2: CPO Testing

Part 2.1 Integrated testing

The main difference between CPO testing and standalone PIC testing is the involvement of EICs and switch ASICs. Optical engines (OEs), which include both EICs and PICs, must be tested, as does the full package that includes the switch ASIC. This more integrated testing requirement adds complexity to CPO testing systems, making them higher in value than silicon photonics testing systems.

However, more integrated testing presents several challenges: 1) the small chip area leaves very limited space for probe placement and alignment; 2) electrical, optical, and RF probes may interfere with one another’s signals; and 3) different signals have different testing speeds, which can reduce overall testing efficiency when one process sits idle waiting for other tests to finish.

Part 2.2 Wafer-level testing

Previously, for standalone EML-based optical modules, most testing was done at the individual component level, followed by testing of the assembled module in the end. During the process, the module’s DSP was frequently configured to ensure the module met performance and production requirements.

In CPO testing, however, there is no DSP. The entire electrical-to-optical conversion process is moved upstream to the PIC, where testing is usually done at the wafer level. This allows all PICs produced from a wafer to be tested in the same batch, a process similar to semiconductor testing. Another benefit of wafer-level testing is that issues can be identified earlier before the PICs are bonded to other higher-value chips and systems, at which point the cost of a failed module would be much higher.

Part 2.3 Coupling

In CPO, there are two types of coupling: edge coupling (EC) and grating coupling (GC). GC is easier and faster to test, but the roadmap itself presents higher insertion loss. Therefore, higher-end applications that are peculiar to loss tend to use EC.

However, EC testing is more challenging. The probes need to be positioned within maximum 5-10um from the chip without touching it, and usually only one probe is used at a time (thus less efficient). Companies such as ficonTEC can command a very high premium for their coupling machines because they are among the most advanced in EC testing.

Part 2.4 Testing time

The most time-consuming part of CPO testing is optical testing. EIC testing usually takes 5-8 seconds per chip, and RF testing takes around 10 seconds. In contrast, optical testing can take over 1 minute per channel/ lane, including the coupling process that aligns the optical probes accurately with PICs. Thus, testing just one 3.2T optical engine with 16 Tx and 16 Rx channels can take almost half an hour.

One approach the industry has been considering to reduce optical testing time is arrayed testing, which allows multiple channels to be tested at the same time. However, this technology has so far been extremely difficult to implement because it requires highly consistent alignment/ coupling across all channels.

Overall, testing a typical wafer can take about over 10 hours, meaning only two wafers can be tested per day. Testing is clearly a bottleneck in CPO production.

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Part 2.5 CPO testing solutions

Currently, there are two major CPO testing solutions in the market. One is a double-sided OE wafer testing machine jointly developed by ficonTEC and Teradyne ($TER). The machine tests electrical signals on the front (upper) side of the wafer and optical signals on the back (under) side simultaneously. It combines ficonTEC’s expertise in optical coupling and testing with Teradyne’s electrical testing expertise.

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Headline benchmark scores look impressive. Token volumes are enormous. Pricing is aggressive. However, the gap with U.S. labs has quietly widened over the past six months. And almost no one is yet to make a profit on the model itself.

This piece is a field guide to that picture. We start with who the players actually are and how they differ. We then look at pricing and the structural reasons Chinese tokens are so much cheaper. Finally, we assess how strong the models really are in terms of generated token quality and what to watch over the next 6 months.

Part 1. Who Are The Players?

There are two camps in Chinese LLMs, and they are playing different games.

Camp 1: startups - four labs, four business models

Four frontier labs anchor the startup camp. They emerged out of academic and finance backgrounds (Tsinghua University, quant hedge fund, etc.), raised aggressively through 2024 and 2025, and converged on a similar technical bet: build frontier models focused on agents and coding (rather than consumer chatbots). The business models, however, are differentiated. Kimi and MiniMax are closest to the Anthropic playbook: frontier coding/ agent models, flagship developer products, and API/ subscription monetization. Zhipu is evolving into a hybrid model: a Palantir-like 2B/2G deployment and services business, an Anthropic-like API and coding-plan business, and a GLM-powered model-supplier and integration-layer role in the OpenClaw ecosystem through Z.AI Coding Plan and AutoClaw. DeepSeek is the outlier - hedge-fund-subsidized, research-led, open-weight by default, and less clearly organized around a conventional commercial frontier-lab end-state. The four labs converged on what to build, not on how to monetize it.

1. Kimi (Moonshot AI)

Founded by Yang Zhilin, formerly of Meta and Tsinghua. Released K2.5 in January 2026, a 1T-parameter MoE model with 32B activated, built through continual pretraining on roughly 15T mixed visual-text tokens atop Kimi-K2-Base. Kimi is arguably one of China’s strongest agentic/ coding models today. K2.6 followed in April 2026, keeping the same 1T/32B-active MLA architecture while improving coding-agent reliability, agent orchestration, and production usability. K2.6 is now the production flagship.

Separately, Moonshot has published the KDA (Kimi Delta Attention) research direction - a linear-attention variant that, in a hybrid 3:1 KDA-to-MLA layout, reduces KV cache by up to 75% and reaches up to 6× decoding throughput at 1M context. KDA is not yet in production K2.5/K2.6 (both use MLA) but signals where Moonshot’s next architectural jump is heading. It has also recently opened a Silicon Valley office to access training data and infrastructure that are hard to obtain inside the firewall.

2. MiniMax (MiniMax)

Designed its model line as agent-first from the earliest releases - while many peers were still bolting agent capabilities onto chat models, MiniMax was already iterating against agent loops. M2.5 launched February 12, 2026 at $0.30/$1.20 per million tokens; the underlying architecture is a sparse MoE with 230B total parameters and only 10B active per token across 256 experts, which is the structural reason the price-performance ratio excels. M2.7 followed on March 18 as MiniMax’s first “self-evolving” release - same architecture and price as M2.5.

MiniMax’s reported 25.4% gross margin (from their full-year 2025 financials, announced March 2026) is a company-wide figure, not specifically attributed to inference - it’s the closest proxy any Chinese model lab has put on the table, but it folds in the consumer-app revenue alongside the API business. Daily token consumption hit ~3 trillion in March, much of it driven by MaxClaw, their cloud-hosted long-running task product.

MiniMax does run consumer apps (Talkie, Hailuo) and they remain meaningful revenue contributors, but management has been explicit that the long-term bet is the agent platform plus API - the consumer surfaces increasingly function as data and distribution feeders into MaxClaw rather than as the end-state business. In that sense MiniMax is dual-track today but heading toward the same Anthropic-style end-state as Kimi.

3. GLM (Zhipu AI)

Spun out of Tsinghua University, Zhipu has the largest research team of any Chinese model lab outside the giants, with around 600 engineers, many of them PhD students, and operates with a more academic culture than its peers. Zhipu sells complete model packages to large 2B and 2G customers (banks, government bureaus) at tens of millions of RMB per contract, a business in which no other Chinese lab competes seriously.

By 2026, however, the API business has overtaken private deployment as the primary growth driver. Roughly 60-70% of API revenue runs through OpenClaw-style agent workloads- Zhipu has shipped two products specifically to strengthen its position: GLM-5-Turbo (March 16, 2026), a closed-source model tuned for OpenClaw scenarios with optimized tool-invocation accuracy, multi-step instruction decomposition, and long-running task stability; and AutoClaw (March 10, 2026), a one-click local OpenClaw installer / desktop wrapper for Windows and macOS.

4. DeepSeek (DeepSeek)

Backed by hedge fund High-Flyer, which gives it both compute access and freedom from quarterly pressure, it is the most research-driven of the four. V4-Pro (1.6T total / 49B active MoE) and V4-Flash (284B total / 13B active) dropped as a preview on April 24, 2026 under MIT license. Both ship with 1M-token context, supported by a hybrid attention scheme that combines Compressed Sparse Attention (CSA) for moderately distant context and Heavily Compressed Attention (HCA) for very distant tokens. At the 1M-token setting, V4-Pro requires only 27% of V3.2’s single-token inference FLOPs and 10% of its KV cache. Commercially, DeepSeek remains less monetization-driven than Kimi, MiniMax or Zhipu. It charges for hosted API usage, but prices V4-Flash extremely aggressively and V4-Pro well below U.S. frontier models, while keeping an open-weight strategy that prioritizes adoption, research leadership and ecosystem influence over near-term licensing revenue.

Revenue-per-employee makes the different business models visible: Zhipu runs labor-intensive on-premise deployments and is the lowest of the three on this metric, MiniMax is in the middle and consumer-product-heavy, and Moonshot (Kimi) is by far the leanest - it builds the model and lets the API do the selling.

Note: Moonshot revenue and headcount are industry estimates; unlike Zhipu and MiniMax, Moonshot has not publicly disclosed audited financials. DeepSeek is omitted because it remains a wholly-owned subsidiary of High-Flyer (the quant hedge fund) and does not disclose revenue or headcount. Industry estimates put its core team at roughly 150-200 engineers, with operating costs effectively absorbed by High-Flyer’s P&L; comparable revenue/employee figures are not meaningful.

Camp 2: The giants - bundling AI into existing platforms

The giants started later, are larger, and play a different game. Their model BUs exist primarily to feed AI features into their existing products - cloud, search, e-commerce, social - rather than to win on raw model quality.

5. Qwen (Alibaba)

Of the five giants, Alibaba has the strongest underlying model. Qwen 3.6 Plus, released April 2, 2026, brought 1M-token default context and agentic coding. Distribution is the long-term advantage - Aliyun’s cloud customers, the Qwen consumer app integrating Ele.me, Fliggy, Taobao, and Alipay. Qwen 4, a fully multimodal model with parameter counts scaling from 100B to trillion-class, is expected in Q2 and Q3.

Alibaba is also pulling ahead in video generation: HappyHorse-1.0, revealed by Alibaba in April 2026 after first appearing anonymously on Artificial Analysis, topped the platform’s blind-test rankings for both text-to-video and image-to-video generation without audio, posting a clear Elo lead over ByteDance’s Dreamina Seedance 2.0 720p. The next-generation bet is full-modal plus 3D - Alibaba intends to use product-image data from Taobao/Tmall to build a 3D-modality moat that the startups cannot easily replicate.

6. Doubao (ByteDance)

ByteDance’s consumer asset: 100M+ DAU on the Doubao app, the highest of any Chinese chatbot. Crucially, the consumer-app model is not the same as the open Doubao on Volcano Engine - the app uses an internally tuned, multi-model router with heavy use of OCR, retrieval, and pre-built workflows. The model is one input, not the product. Volcano Engine is, by most accounts, the only Chinese MaaS business operating at positive gross margin, achieved by pricing aggressively in commoditized segments and charging in protected ones.

ByteDance’s real strength sits in multimodal generation rather than the base language model: Seedance 2.0, released February 2026, remains a credible video-generation product (with multiple free entry points via the Doubao app, Dreamina, and Jimeng AI), even after Alibaba’s HappyHorse took the top of the leaderboards. The base Doubao language model is publicly acknowledged to lag the Chinese first tier; ByteDance’s internal roadmap reportedly targets a native multimodal model in mid-2026 (benchmark target: Kimi K2.5-class) and a more ambitious frontier push by year-end (target: Gemini 3-class). Talent attrition to startups is a real, ongoing risk on the language-model side.

7. Hunyuan (Tencent)

The weakest of the five giant models. Tencent’s bet is distribution (WeChat, QQ, gaming), rather than model strength. Cloud business is third-tier in China.

8. Ernie (Baidu)

The earliest Chinese LLM player, now visibly fading. Consumer presence has eroded; cloud share is small; the model lags on every dimension that matters.

9. MiMo (Xiaomi)

The fifth giant, alongside Alibaba, ByteDance, Tencent, and Baidu - but with a hardware-attached distribution model rather than a cloud-based one. Xiaomi distributes its models for free on OpenRouter and integrates them into phones, IoT, and EVs. The model exists to make the device better; not to operate as a standalone P&L. This puts Xiaomi in the same strategic camp as the cloud giants: the model is a feature, not the product.

By 2024 to early 2026, the giants concentrated their R&D on general features - search, Q&A, and long-form writing - to feed AI Bot products. By Q1 2026, however, they realized the bet had been wrong: the long-term value sits in agents and coding, where the startups had a head start. The pivot is now on, and the window to catch up is narrow.

Figure 1. China LLM landscape. X-axis: 2B (left) -> 2C (right). Y-axis: Agent (top) -> Chatbot (bottom). Bubble size approximates token consumption.

Note: MiniMax’s bubble size can be misleading - that ~3T tokens per day in March is heavily skewed by MaxClaw, where each task can run for hours. Token volume is no longer a clean proxy for model quality.

Part 2. How much do they cost?

2.1. The huge price gap

Chinese models are dramatically cheaper than their international counterparts - typically 3 to 10x lower per token, occasionally 100x at the budget end. The full picture:

Sources: U.S. vendor pricing from Anthropic, OpenAI, and Google official API price pages (updated May 2026). Chinese vendor pricing from each provider’s console or official pricing page (Aliyun Model Studio for Qwen, Volcano Engine for Doubao, Z.AI for GLM, Moonshot/Kimi API Platform, MiniMax Open Platform, DeepSeek Open Platform, Tencent Cloud Hunyuan, Baidu AI Cloud Qianfan). Gemini 3.1 Pro shows <=200K-token / >200K-token pricing; DeepSeek V4-Pro shows current discounted pricing with list pricing in parentheses. Gross-margin claims are vendor-disclosed where stated and otherwise inferred from operator interviews.

Three things stand out. First, frontier U.S. models are priced more like margin-seeking products, while most Chinese models are still priced for adoption, cloud pull-through, or ecosystem capture. Second, many premium Chinese models are priced as cloud loss-leaders by their parent platforms, with Doubao for Volcano Engine, Qwen for Aliyun, and Hunyuan for Tencent Cloud as the clearest examples. The model is the “bait.” Third, MiniMax is the only Chinese startup with a disclosed company-level gross margin that suggests improving unit economics, but the figure is not a clean inference/ API margin. Zhipu’s overall business is profitable on the 2B/ 2G deployment side, but its API/ inference economics are still harder to verify. Everyone else is buying market share on inference.

2.2 Why are Chinese tokens so cheap?

The conventional answer - cheap electricity and cheap engineers - is wrong. Both inputs do help, but they are not why a Chinese inference token costs a fraction of an American one. Four real reasons:

a) Inference runs on consumer GPUs

U.S. labs serve frontier models from H100 and B200 clusters. Chinese serving runs heavily on consumer cards (RTX 4090s, 5090s) because export controls cut access to data-center-grade silicon. Those cards generate tokens fine; what they do not do well is concurrent serving at scale. This is exactly why GLM-5 users complain about lag, stalling, and mid-stream cutoffs. The price reflects the hardware tier.

b) Architecture-level cost cuts

Chinese models lean hard into sparse MoE plus attention-efficiency techniques (MLA, compressed/sparse attention, and emerging linear-attention variants) to reduce active FLOPs, KV-cache size and long-context serving cost. Linear attention can reduce full-sequence attention toward O(N), while compressed/sparse schemes reduce practical decoding cost and memory rather than fitting one clean asymptotic formula. U.S. frontier models have largely stuck with full attention because it preserves capability on long-context, complex reasoning. The Chinese trade is explicit: cheaper tokens for slightly worse capability on the hardest tasks. DeepSeek V4’s hybrid Compressed Sparse Attention, released in late April, is the most aggressive version of this trade yet.

c) The advertised context window is not the served context window

A model marketed as 200K context often runs against a smaller cap in production to keep latency and stability acceptable. The number on the spec sheet is a ceiling, not a guarantee.

d) Aggressive subsidy and strategic pricing

The final reason is not technical at all: many Chinese model prices are strategic rather than cost-reflective. Cloud platforms price models as loss-leaders to drive traffic into Aliyun, Volcano Engine, Tencent Cloud or Baidu Qianfan. Startups price aggressively to acquire developers, generate usage data, and build ecosystem mindshare before the market consolidates. In other words, cheap Chinese tokens are not always cheap because the marginal cost is structurally lower; they are often cheap because the provider is willing to monetize elsewhere - through cloud pull-through, enterprise deployment, subscriptions, data, or future platform lock-in.

Distillation, which will be discussed in Section 3.3, also helps indirectly, it reduces the R&D and training cost required to reach benchmark-competitive capability, but it does not by itself lower the marginal cost of serving each output token. Token price is still mostly determined by inference architecture, hardware, context length, utilization and subsidy strategy.

Bottom line: Chinese tokens are cheap because the hardware stack is cheaper or more constrained, architectures are optimized for lower active compute, served context is often below advertised context, and many providers are pricing strategically below fully loaded cost.

Part 3. How smart are they?

3.1. The benchmark performances look close

Every Chinese frontier model now scores within a few points of Claude Opus 4.6 on standard coding and agent benchmarks. The leaderboards look almost flat: On SWE-Bench Verified, if we put the latest Claude Opus 4.7 aside first, the spread between the top five models is under two points. Read the numbers literally and the U.S. lead is nearly gone.

* For GPT-5.5 and GPT-5.4, the SWE-Bench Verified number comes from Vals’ uniform-harness SWE-Bench run, not OpenAI’s own launch page.

Sources: Anthropic / AWS for Claude Opus 4.7; Anthropic for Claude Opus 4.6; OpenAI for GPT-5.5 and GPT-5.4 SWE-Bench Pro / Terminal-Bench / context-window data; Vals for uniform-harness SWE-Bench Verified scores on GPT-5.5 and GPT-5.4; Google DeepMind model card for Gemini 3.1 Pro; Moonshot/Kimi for Kimi K2.6; MiniMax for M2.7; DeepSeek model card for V4-Pro Max; Qwen official release blog for Qwen 3.6 Plus; and Z.AI / GLM model cards for GLM-5/5.1. Scores are not perfectly apples-to-apples because vendor-reported results may use different harnesses, reasoning budgets and scaffolds.

3.2. But real gaps exist

The gap is obvious on the dimensions benchmarks don’t measure well. Five aspects matter most:

a) Context window

Claude Opus 4.7 (and 4.6 before it) ships with 1M tokens. Most Chinese leaders sit at 200K, and the served window is often smaller than the advertised one, production systems quietly cap context to keep latency and stability acceptable. DeepSeek V4 and Qwen 3.6 Plus claim 1M, but production reliability at that length is unproven. Long-context capability is not something you can distill - it requires pre-training investment Chinese labs largely have not made.

b) Long-context recall - the “needle in a haystack” test

ontext window is the advertised ceiling; long-context recall is whether the model can actually use that window. Pulling a specific fact out of a 500K-token input requires native long-context training, not fine-tuning. U.S. frontier models are generally ahead on long-context reliability. Chinese models degrade sharply once context exceeds their training distribution - which is why the 1M-token claims from DeepSeek V4 and Qwen 3.6 Plus need to be discounted in production.

c) Hallucination

Frontier U.S. models hallucinate at roughly under 1% on standard factual tasks (per Vectara’s HHEM-2.1 leaderboard and operator-reported failure rates). Chinese leading models cluster in the 3-5% range. The gap is several-fold in user-visible failure rate and widens as tasks grow longer. For agent loops, where a hallucination in step three poisons every subsequent step, the difference compounds quickly.

d) Multi-turn precision

On a generic single-shot question “recommend things to do in Beijing” - Chinese models match the U.S. frontier. The gap opens when a user drills into a specific detail across multiple turns. Chinese leaders tend to drift, repeat themselves, or output something approximately right rather than precisely right. Operators report this as the single most visible weakness in production.

e) Native multimodality

Frontier U.S. models train vision, audio, and language jointly from scratch. Many Chinese models still bolt vision onto a language base. Qwen 3.6 Plus and Kimi K2.5/K2.6 are the closest exceptions. The difference is most visible on tasks requiring fine cross-modal grounding - reading a screenshot, generating code from a design mock, parsing a chart.

3.3. Distillation: one reason behind the high scores

Distillation appears to be an accelerator for several Chinese labs, especially on benchmark-facing capabilities. The architecture has converged. Nearly every Chinese open model is now a variant of DeepSeek’s MoE design with minor precision tweaks. Pre-training, the most expensive part of model building, is largely skipped. Instead, the workflow looks like this:

• Take an open architecture (typically DeepSeek’s).

• Fine-tune on data distilled from Anthropic, OpenAI, or Google.

• Run reinforcement learning with carefully tuned rewards.

The first two steps mean Chinese models inherit the answers and patterns of frontier U.S. models. The third is where labs differentiate, and the differences are surprisingly small. Most of what separates Chinese labs today is reward-function tuning at the RL stage: whether a correct answer is worth 1.0 or 1.5, whether a failed tool call costs 0.5 or 1.0. That kind of tuning produces fast, visible benchmark gains, but it does not build new capability, it borrows it.

Distillation explains the leaderboard convergence. It also explains why labs that invest little in pre-training (Zhipu, MiniMax) score nearly as well as labs that invest a great deal (DeepSeek). Taking the shortcut works.

However, this shortcut has a shelf life。

Anthropic, OpenAI, and Google have begun deploying countermeasures - rate limits, output watermarking, prompt fingerprinting, to detect and disrupt distillation. Insiders estimate the practical window before distillation becomes meaningfully harder is roughly six months.

That is why Kimi has opened a Silicon Valley office, why Xiaohongshu is hiring infrastructure engineers in California, why MiniMax is searching for offshore compute. The Chinese labs are racing to build their own data and infrastructure stack before the door closes. If they succeed, they keep pace. If they don’t, the next two model generations will look meaningfully weaker than this one, and the structural gap will become visible.

3.4. The international gap: structural, not transient

On three dimensions the gap with U.S. frontier models is widening, not closing. The first is pre-training data - the U.S. labs have a real, working data flywheel from massive consumer products and a healthy enterprise market. China’s B2B environment is less willing to pay for AI services, which forces Chinese models toward consumer monetization, which produces less useful training data. The second is compute - U.S. labs have unconstrained access to the latest silicon. Chinese labs do not, and the export-control regime is tightening rather than loosening. The third is the engineering culture around RL - Anthropic’s edge in agent loops and tool use comes from years of accumulated, hard-to-document engineering experience that distillation cannot transfer.

3.5. Who’s actually leading

Now the big question: who is actually leading among the Chinese labs? This has been hard to answer because benchmark performance looks similar. But real differences do emerge in actual usage, especially in coding and agentic workloads. In the section below, we will display our assessment of how well each model actually performs, and rank them from top to bottom, based on a synthesis of information and inputs from multiple primary sources. We will also discuss our projection on what’s going to happen in the next 6-12 months within the Chinese AI model space.

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In last week’s note, we reviewed Lumentum’s history and the factors that helped build its high-power laser capabilities. This note takes a deeper look at Lumentum’s advantage and provides a clearer picture of how far ahead Lumentum is versus peers and why I believe this advantage is sustainable.

Part 1: How Far Ahead Is Lumentum?

There are 6 stages in high-power laser production:

• Internal Qualification (Stage-1): testing pure device physics in the vendor’s own lab. The test scope typically includes the chip’s ability to survive high temperature, acceleration factors, and operational lifetime under different operating conditions (HTOL reliability testing, etc.). This stage usually takes 12-18 months to complete.

• Hyperscaler Qualification (Stage-2): involves testing lasers integrated into the customer’s CPO switches and conducting system-level validation in the hyperscale environment. The test scope typically includes power cycling, thermal cycling, long-term stability, and interoperability. A vendor cannot enter Stage 2 until it has approved completion for Stage 1. This stage usually takes 18-24 months.

• Pilot: typically begins about 3 months after the vendor passes Stage-2 qualification. At this stage, production volume is still limited, usually at around 1-10K units/ month.

• Low-rate production: is reached after the vendor resolves initial yield issues, which typically takes around 6-9 months after pilot. At this stage, production volume increases to roughly 10-50K units/ month.

• High-yield production: can be reached after roughly another 6 months of ramp. At this stage, the vendor is able to produce ~100-500K units/ month. Reaching this level means that the company needs to have received meaningful orders from at least one hyperscaler.

• At-scale production: refers to production levels >500K units/ month. This stage can occur 9-12 months after high-yield production, although the exact timing depends heavily on when the vendor has sufficient orders to justify scaling capacity to this level.

Lumentum: completed Stage 2 in early 2024 and advanced to low-rate production by end of 2024. The company then reached high-yield production (100K units per month) by 2H25, as Nvidia began shipping its CPO switch products to customers. Today, Lumentum is in the “at-scale production” stage with a production level exceeding 500K units per month, to support Nvidia and other customers. Its progress is well ahead of the second player and is currently the only vendor reaching mass production.

Lumentum has now moved the goalposts to have demo-ed an 800mW laser at 50°C with 200kHz linewidth, with sampling expected by late 2026.

Coherent: is still in Stage 2 qualification and is expected to reach pilot by 3Q26. Based on this timeline, the company appears to be at least two years behind Lumentum, which reached pilot at around mid-2024.

Coherent is expected to reach high-yield production by 2H27. Only at that point would it begin to have a meaningful impact on Lumentum, as volume of over 100K units per month would start to matter commercially. This also means Lumentum’s volume position should remain relatively secure until at least late 2027. Even then, Coherent would likely need another year (until 2H28) to reach the at-scale production level that Lumentum has today.

Frankly, I think this lead in the development cycle is Lumentum’s most important moat. It is not that other companies cannot develop the high-power laser technology. Rather, the challenge is that there is no obvious shortcut through the qualification, validation, yield improvement, and scaling-up process required to reach commercial production. This gives Lumentum a tangible time-to-market advantage to continue iterating its product research, scaling its productions, and integrating into client product roadmaps, all of which help reinforce its market position.

AAOI: is currently around 18 months away from passing Stage-2 qualification, which puts it about four years behind Lumentum. The company is not very likely to reach high-yield production before 2029.

Sumitomo: is also around 18 months away from passing Stage-2 qualification, and thus about four years behind Lumentum. It is also not expected to reach high-yield production before 2029.

One thing to note here is that hyperscaler relationships can make a meaningful difference for Stage 2. In many cases, vendors face a waiting queue of ~12 months before they can engage with the right hyperscaler engineering team for Stage 2 validation. Vendors that already have strong trust and relationships with hyperscalers may be greenlit ahead of other suppliers in the queue. AAOI’s existing relationships with hyperscalers through prior transceiver contracts and Suminoto’s strong relationship with Nvidia should help both of them accelerate their progress for Stage 2 with relevant customers.

Part 2: How Competitive is Coherent?

Similar to Lumentum, Coherent also has a strong high-power laser heritage, particularly in pump lasers for undersea amplifier markets, where reliability requirements are extremely high. On paper, Coherent offers a very competitive solution. Its upcoming high-power CW laser is marketed to deliver 400mW of optical output power at 55°C, with a very narrow linewidth of 200kHz. By comparison, Lumentum’s current solution outputs 350mW at 50°C with a linewidth of 500kHz. The benefit of the very narrow linewidth is that it can help reduce noise and improve signal integrity.

Another advantage for Coherent is that it has a strong vertical integration capability. It can package its 400mW laser chip into a complete ELSFP module using its own connectors and PM fibers, as Coherent is itself a broad component supplier with strong assembly capabilities. Our conversations with experts from Broadcom indicate that customers value module-level solutions, as they can significantly reduce integration time, engineering effort, and POC/ testing costs.

The company has also sharpened its execution under the new CEO since mid-2024. It has refocused its strategy on AI and divested non-core assets, and completed its 6-inch transition a year ahead of schedule and has now reached full production.

The key risk for Coherent, however, is how well it can ramp high-power CW laser production at its new 6-inch fab facility. The larger 6-inch InP wafers introduce challenges in material uniformity, defect control, and thermal management. Variations in quantum well thickness can make power output non-uniform; center-to-edge differences in temperature and deposition rates are also harder to manage at 6-inch scale.

In addition, all prior yield improvements on 6-inch were on EML products that existed on 3-inch wafers. The 400mW CW laser is a brand-new product with a much higher power level. Higher power creates heat stress, electromigration, and facet degradation. These issues are less problematic for EML that has lower power level at 5-15 mW - a 5% slope variation can be absorbed with slightly higher current and TEC can help correct the wavelength drift. However, a 5% lower slope on a 6-inch wafer would cause the 400mW CW laser to fail specification entirely.

We were told by a major CPO laser customer that reliability is the single most important qualification criterion for high-power lasers. The blast radius of a failed laser or optical module in a data center is enormous, and high-power lasers are notoriously difficult to manufacture reliably. Whether Coherent can produce its high-spec lasers with high reliability will determine how well its products sell to customers and how much share it can capture from Lumentum. We think it will take at least 12 months before we can have greater confidence in Coherent’s production ramp.

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Part 3: Which Vendor Does Broadcom Prefer?

So far, the market has been fairly clear on Lumentum’s dominant position with Nvidia. But what about Broadcom? Will they use internally produced lasers?

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Phase 1: JDSU

Lumentum traces its origins to two pioneering photonics enterprises: Uniphase Corp formed (founded in 1979) and JDS Fitel (founded in 1981). Uniphase was as a supplier of commercial lasers and subsequently optical transmission products. The company became publicly traded in 1992. JDS Fitel was as a pioneer in products for fiber optic networking. In 1999, JDS Fitel merged with Uniphase to become JDS Uniphase (JDSU), creating one of the largest optical networking companies in the world.

In 2001, the company recorded a massive loss of $56 billion on revenue of just over $3 billion. This was largely due to the bursting of the “internet bubble” - as it took a $50 billion goodwill impairment charge following the collapse in the valuations of companies it had acquired over the prior one to two years at peak telecom-bubble prices. The losses were followed by several years of continued downsizing, with headcount falling from 29K in 2001 to 5.5K in 2023. Despite the downturn, however, the company still completed the landmark acquisition of SDL in 2001, adding semiconductor laser technology to its portfolio. In 2001, the company also acquired IBM’s optical transceiver business for $100 million. In 2003, the company acquired TriQuint’s undersea pump laser business.

In 2005, the company made a key acquisition of Acterna for $760 million. Acterna was a leading provider of broadband and optical test and measurement solutions, and the acquisition created an entirely new business segment (CTM) that went on to become JDSU’s largest revenue contributor. In the same year, it also acquired Agility Communications and Lightwave Electronics. Agility added broadly tunable, long-wavelength laser technology for metro and long-haul applications, while Lightwave contributed high-power pulsed solid-state laser products and technology, expanding the company’s addressable market into micromachining.

In 2007, the company acquired Picolight, which brought VCSEL technology.

The company was affected by the 2008 financial crisis, with FY2009 revenue down 16% yoy. Management responded with significant cost-cutting measures and eventually returned the business to profitability in FY2011. During this period, however, the company continued to invest in R&D, increasing spending from $170 million in FY2009 to $240 million in FY2011.

In 2014, the company acquired Time-Bandwidth Products, which again strengthened its high-power pulsed solid-state laser capabilities. The company also began laying the groundwork for its separation in this year. Finally in 2015, the company executed the separation of Lumentum as an independent publicly traded company, while the remaining entity was renamed Viavi Solutions.

At the time of the separation, the company operated in three main segments: 1) Communications Test and Measurement: providing testing instruments for fiber-optic networks such as handheld reflectometers and optical spectrum analyzers; 2) Communications and Commercial Optical Products (CCOP): main products included narrow-linewidth DFB lasers, tunable lasers, optical amplifiers, modulators, optical switches, and high-power lasers for 3D sensing; 3) Advanced Optical Technologies: products include optically variable pigments, holographic labels, and microtaggants. The CCOP segment, which later spun off to Lumentum, reported ~$800 million revenue in FY2014.

In terms of leadership and culture, founder Jozef Straus built an engineering-driven culture centered on innovation. JDSU emphasized a “design-in” strategy, valuing long-term collaboration with customer engineering teams.

Phase 2: Early Years as a Public Company

In 2015, the company completed the spin off its CCOP business into Lumentum. The remaining parent company, JDSU, was simultaneously renamed Viavi Solutions. The two reportable segments of Lumentum at inception are Optical Communications and Commercial Lasers.

In 2017, the company made a pivot into selling more 3D sensing for consumer electronics, leveraging the VCSEL technology from the earlier Picolight acquisition during the JDSU era. By FY2018, its 3D sensing products had been adopted at scale in flagship smartphones for facial recognition, and Apple accounted for ~30% of total net revenue in that year.

In 2018, the company completed the acquisition of Oclaro for $1.8B, which is a supplier of coherent optical components and modules using a vertically integrated module. It has more than three decades of innovation in laser tech and photonics integration with core strengths in: 1) InP & LNO expertise, 2) manufacturing processes including epitaxy, lithography, and etching, and 3) photonic integration around InP materials, and the ability to combine multiple functions on a single InP chip. According to company filings, it has six major product lines:

• Client-side transceivers: ranging from 25G to 400G

• Line-side transceivers: including 100G/200G tunable-laser-based products, integrated photonics, and coherent pluggables

• Coherent transponder modules: spanning 100G, 200G, 400G, and 1.2T

• Tunable laser transmitter assemblies: iTLA and iTXA, including narrow-linewidth tunable lasers paired with MZMs

• Lithium niobate (LNO) modulators: covering 100G, 200G, and 400G

• Discrete lasers and receivers: including DFB and EML laser dies, and PIN/APD receivers

In 2019, the company undertook several divestitures, aiming to exit more commoditized businesses and refocus on differentiated components and lasers. It sold its datacom transceiver module product line to CIG and discontinued its LNO modulator product line.

Phase 3: Marching into AI Datacom

In 2021, the company once entered into a merger agreement with Coherent, but ultimately lost the deal to II-VI and received a $218 million termination fee. In the same year, the company acquired NeoPhotonics, a provider of ultra-pure light tunable lasers and optical components used in coherent applications. The transaction was closed in August 2022. I have a separate section below to go into NeoPhotonics’ history in greater details.

In 2022, the company acquired IPG Photonics’ telecom transmission product lines, including coherent DSPs, ASICs, and transceivers, helping it expand into the higher-value DSP layer.

In 2023, the company reentered the datacom optical module market by acquiring Chinese module maker Cloud Light for $750 million. Later that year, it reorganized its reportable segments from the legacy Optical Communications and Lasers structure into two new end-market-focused segments: Cloud & Networking and Industrial Tech. Cloud & Networking includes the company’s telecom and datacom product lines, including transceivers, high-speed laser transmitters, PICs, photodiodes, high-power lasers, VCSELs, coherent pluggables and the underlying ultra-narrow-linewidth lasers and components. Industrial Tech consists of the legacy Lasers segment plus the Industrial and Consumer product lines previously reported under OpComm.

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Bonus Section: Neophotonics History

One important acquisition Lumentum made in the past was its acquisition of NeoPhotonics in 2021. The deal greatly added Lumentum’s capabilities in high-power tunable lasers, which are a key enabler of the company’s high-power laser product leadership in CPO.

In today’s bonus section, I will provide a four-part analysis of NeoPhotonics’ history, along with a discussion of one important executive Lumentum brought in from NeoPhotonics who has played a major role in the company’s data center interconnect business.

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Part 1: EML Capacity

2025: 90-100 million units of 100G EMLs

Breakdown by providers:

• LITE: 30M

• AVGO: 15M

• COHR: 20M (for internal use)

• Mitsubishi: 15-20M

• Sumitomo: 15-20M

Top-down reconciliation:

• In 2025, 800G transceiver shipments are about 20M units. ~40% are single mode EML modules (or 8M units), which would require 64M 100G EML lasers

• In 2025, 400G transceiver shipments are 15-20M units. ~30% are single mode EML modules (or 5-6M units), which would require 20-25M 100G EML lasers

2026: 200-250 million 100G/200G EMLs

Breakdown by providers:

• LITE: 80M (60M 100G EML + 20M 200G EML)

• AVGO: 50M

• COHR: 30M (for internal use)

• Mitsubishi: 25M

• Sumitomo: 30M

Top-down reconciliation:

• In 2026, 800G transceiver shipments are expected to reach 40M units. ~50% are expected be single mode EML (or 20M units), which will require 80M 100G EML lasers, or 40M 200G EML lasers. 200G and 100G EMLs have similar die sizes

• In 2026, 1.6T transceiver shipments are expected to be 20M units. ~70% are expected to be single mode EML modules (or 14M units), which will require 80-90M 200G EML lasers

• There will also be 100G EMLs needed for 400G single mode modules

Overall, 200G EMLs remain in severe short supply, and this is unlikely to be resolved in the near term. I’ll provide a detailed analysis of the supply chain rationale in Part 3.

Part 2: 70mW/100mW CW Laser Capacity

2025: ~100 million units of 70mW/100mW CW lasers

Breakdown by providers:

• Yuanjie: 20-30M

• Sumitomo: 20-30M

• LITE: 20M

• AVGO: 10-15M

• And others

2026: ~150M units of 70mW/100mW CW lasers

Breakdown by providers:

• Yuanjie: ~50M

• Sumitomo: ~40M

• LITE: 20M

• AVGO: 20M

• Landmark: 20-25M (around 2/3 are 100mW)

• Furukawa: 16M

Top-down reconciliation:

• In 2026, 800G transceiver shipments are expected to reach 40M units. ~50% are expected to be sipho (or 20M unitsd), which would require 80-160M CW lasers

• In 2026, 1.6T transceiver shipments are expected to reach 20M units. ~25% are expected to be sipho (or 5M units), which would require ~20M 100mW CW lasers

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Part 3: EML Capacity Bottleneck

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Near-term, however, a narrow arbitrage window exists. The market has largely moved past the 4Q25 capex revision scare, and the setup for the next few quarters is highly favorable:

1. Demand & Pricing: Agent-driven demand is lifting 1Q26 lease pricing (+~30%) and adoption rates for both Blackwell and legacy Hopper cards, offsetting GB200 ramp friction.

2. Financials Inflecting: 1Q26 revenue is tracking to beat low-teens guidance. As topline growth outpaces front-loaded D&A, OPM should inflect low-to-high through FY26.

3. Fundable Milestones: The 2026 active power target (1.7GW) and 2027 EoY ARR ($30B) appear fully fundable under current cash and debt capacity.

Key miss risks: utilization stalling below 60% (vs. ~85% now), lease pricing declining ~50% YoY (vs. a normalized 15%~20% annual decay).

FY28 estimates: $33B revenue, 20% OPM, $6.6B operating profit, -$3.6B net interest expense at 6%, $3.0B net income. Implied ~19x FY28 P/E, 1.7x P/S with stock price at $110, Apr 13th.

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Part 1: The Setup

Coreweave (CRWV) dropped 18.5% after the 4Q25 print - the market punished heavy capex guidance and a weak bottom line. This reaction marked a regime shift: the market is no longer rewarding datacenter construction narratives and is now pricing AI infrastructure on ROI terms.

The capex narrative from 4Q25 has been substantially de-risked. CRWV secured $8.5B in collateralized financing (DDTL 4.0), received $2B booking from Meta, and proposed a $3.0B convertible senior notes. Current cash position and organic CFO can support buildout to 2-2.5GW without additional equity dilution. The capex ghost story is digested.

We think CRWV is still a meaningful beneficiary of the current AI wave. Although the long-term business model might be still under doubt at the moment (yes, we do share concerns on L/T execution, competitive positioning, and balance sheet financing risk) - but the next few quarters present a tradeable setup where the supply/demand dynamic temporarily favors the stock.

The short-term case rests on three pillars:

1. Demand (Agent Tailwind): 1Q26 revenue is tracking to beat low-teens guidance, as agent-driven workloads push lease pricing and adoption rates higher across both new and legacy GPU generations.

2. Supply (High Visibility): The 2026 active power target (1.7GW) and 2027 EoY ARR ($30B) are fundable under current capacity, anchored by management’s claim that FY26 is virtually sold out.

3. Profitability (Margin Inflection): OPM is set to inflect low-to-high through FY26 as accelerated topline growth finally catches up to the front-loaded D&A from the recent peak capex cycle.

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Part 2: Demand - Agent Tailwind

Hopper lease pricing has started to soften again after brief stabilization. Usually, this is the fundamental demand dynamic of GPU leasing: each generation faces accelerating economic depreciation as newer silicon enters the market. But the near-term demand picture, however, is strong.

Agent workloads are scaling rapidly and driving incremental lease demand across GPU generations. Open Cloud adoption and enterprise agent deployments generate order flow that is visible in both pricing and adoption metrics for 1Q26. The backlog (~$69B total) reflects broadening customer diversification - OpenAI at $22.4B, Meta at $16.3B (including the April $2.1B booking), NVIDIA at $6.3B - beyond the historical MSFT concentration (62% of FY24 / 67% of FY25 revenue).

New logos (Anthropic, Midjourney, Cursor) are real but remain long-tail contributors. The broader demand dynamic is robust and expanding: as model developers aggressively push to expand their TAM, they are increasingly prioritizing the flexibility and rapid deployment (time-to-market) offered by standard public cloud architectures and bare-metal GPU leasing. This pursuit of agility effectively broadens the overall market size and injects massive liquidity into the compute ecosystem. While this expanding TAM and hardware liquidity naturally invite competition - NBIS is already targeting the same anchor customers (MSFT $17.4-19.4B, Meta $3B, plus $2B NVIDIA investment) - it fundamentally validates a much larger, highly active market appetite for standardized infrastructure.

Part 3: Supply - Nvidia’s “Favorite Son”

CRWV captures approximately 10-15% of NVIDIA’s annual rack shipments for the foreseeable future. This supply relationship is the single most tangible near-term advantage - priority allocation in a supply-constrained environment.

Estimated active GPU holdings as of 4Q25: ~180K Blackwell, ~300K Hopper, ~50K Ampere. Outstanding orders: ~500K Rubin (likely to revise upward), ~500K Blackwell, ~350K Hopper. 1Q26 is expected to add ~130K Blackwell cards, bringing active power from 850MW to 1.1GW, with year-end target at 1.7GW. 2028 above 3GW.

In order to make the 2027 EoY ARR target of $30B achievable, CRWV needs to issue approximately $20B in additional debt beyond current commitments (a target we view as highly feasible, see below). This is directionally consistent with the trajectory if utilization holds, though execution risk on that quantum of issuance is material.

Concerns over the long end of the curve slightly softened but not eased, shown buy CDS curve. Excluding self-amortizing contract-backed debt and OEM vendor financing, CRWV has no major debt maturities before 2029, leaving its pre-2028 maturity profile clean.

We believe the funding gap is primarily a 2028-2030 concern; liquidity through 2026-2028 appears manageable.

• A 5GW buildout over the next 5 years requires approximately $200B of total investment. Current outstanding debt: $21B (4Q25). At 60-70% CFO/revenue margin, cumulative operating cash flow reaches $90-110B - a funding gap of at least $90B that must be bridged by additional debt issuance.

• But for approaching the 2028 target, we estimate ~$20B in incremental financing is required (YTD having already raised ~$11.5B via a $3B convertible note and an $8.5B secured loan). The pace of capital formation is highly favorable. Combined with robust advance bookings (e.g., Meta’s $2B prepayment), we estimate CRWV can generate ~$40B+ in cumulative operating cash flow (CFO) from 2026-2028, largely bridging this gap

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Part 4: Profitability - The Unit Economics

FY25 gross margin: ~70%. OPM: ~13%. Management’s long-term OPM target of 25-30% requires legacy GPUs to maintain 60-80% utilization in years 4-6 of deployment.

Under a more realistic utilization curve - 70% / 60% / 60% in years 4, 5, 6 - company-level returns converge to breakeven at late 2027:

• 1GW Blackwell deployment: total infrastructure capex ~$36B (based on broker estimation), cumulative 6-year revenue ~$55B (flat pricing), implied IRR 18%. Even at constant pricing over the full 5-year depreciation schedule, IRR reaches only 21%.

• Current WACC: 9.36%. The spread between unit IRR and WACC is thin before OpEx and almost vanishes after. After S&M (~2%) and G&A (~3%), net contribution compress to the low-single-digit level. Over the last 12 months, CRWV has compressed its WACC by 300bps and continues to prioritize further reduction.

The worst of the margin compression is behind us. D&A headwinds have peaked, paving the way for long-term margin stabilization. D&A as a % of revenue breached 52.2% in 4Q25 (up from a historical ~45%), creating significant OPM pressure (~10% quarterly dilution). This was primarily driven by peak capex from the massive B-series GPU intake. Going forward, capex will normalize (Next-1Q active power capex at ~$35-40B/GW) and the blended depreciation ratio will settle at 12-14% ($20B over 5-7 years + $15B over 10 years). Consequently, D&A % Rev should stabilize at 50-55%. We believe the market has largely moved past the 4Q25 capex revision scare.

We also expect NeoCloud margins to expand, driven primarily by accelerated topline growth outpacing D&A. For comparison: hyperscaler cloud businesses operate at 30-45% OPM and 50-60% EBITDA margin. CRWV’s post-depreciation GAAP gross margin is 15-25%, OPM 10-20%. FY25 net interest expense: ~$1.3B at a 8.4% effective rate. Breakeven point is expected around late 2027.

Part 5: Valuation

S/T FY26: $13B revenue, 15% OPM, $1.9B operating profit, -$2.2B net interest expense, -$0.2B net income.

L/T FY28:$33B revenue (assumes 3.6GW achieved out at 2028 of 6GW 2030 target), 20% OPM, $6.6B operating profit. Additional 2.5GW capex funded by ~$20B incremental debt. Net interest expense of -$3.6B at 6% (decrease from current 8.8%). Net income ~$3.0B. Implied ~19x FY28 P/E, 1.7x P/S with stock price at $110, Apr 13th.

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Part 1: Scale-Up

TPUv7 uses a 3D torus architecture to connect 9,216 TPUs in its ICI scale-up domain. Each rack is logically arranged as a 4x4x4 cube, and every outward-facing TPU surface has an optical connection - there are in total 96 outward-facing surfaces, since each of the cube’s six faces contains 4x4 links.

The diagram below provides a clear conceptual view of the 64-TPU configuration.

But how do you scale from 64 TPUs in a single rack to 9,216 TPUs in the entire scale-up domain? This is where OCS comes in - the switch is used to route traffic across 144 racks.

As we discussed in our previous article, OCS accepts only optical signals as inputs. Thus, each of the 96 surfaces is paired with one 800G FR transceiver, which converts the electronic signals inside the cube into optical signals. Those signals are then sent to the OCS for routing.

The interconnection follows a simple rule: TPUs on the same axis are connected through the same OCS. Each cube consists of 48 different axes, with 16 along each of the X, Y, and Z dimensions, as shown in the diagram above. As a result, TPU 4,4,1 can connect to TPU 4,1,1 across all 144 cubes (including its own) through the same Y-axis OCS - call it OCS 4,Y,1. Similarly, TPU 4,2,1s and TPU 4,2,4s are connected through the Z-axis OCS 4,2,Z.

There are no cross-connections across different axes. That means TPU 4,4,1 can never connect to TPU 4,3,1 through the OCS/ optical links. Instead, they communicate through the 800G copper links within the cube. Since there are a total of 48 axes, 48 OCS units are used in the cluster.

Someone may wonder: why 144 racks? The answer comes down to the maximum number of effective ports on the OCS switch. Before 2026, deployed OCS systems were from the 176x176 platform. At the time of TPUv7 deployment, the 144x144 variant was mature enough for mass production, and thus the ICI domain could scale to a maximum of 144 racks, as each port links to one rack.

The calculation above assumes that the optical links from the cubes are unidirectional. In other words, TPU 4,4,1 in each cube can only transmit signals, while TPU 4,1,1 at the other end of the axis can only receive them. If the optical links are bidirectional, which is supported by Google’s custom-designed 800G FR transceivers, then you would either need to double the number of OCS units (from 48 to 96) or use a larger OCS, such as a 300x300 variant to interconnect the 144 racks. In the latter case, each OCS would use 288 ports on the input as well as output sides, with two of those ports connected to two different TPUs in the same rack (and the same axis) - for example, TPU 4,4,1 and TPU 4,1,1, since both can now transmit signals.

A very well-known semiconductor research firm claimed that TPU v7 clusters use 144x144 OCS switches for bi-directional links, which I believe is incorrect.

With the information above, we can now calculate the attach ratios. For a 9,216-TPU cluster, 48 OCS units are required - implying a TPU-to-OCS attach ratio of 192:1. We estimate total TPU installations at around 2.5-3 million units in 2026 (installation is a different concept than shipments that we discussed in our previous TPU article) - which would translate into demand for 13-16K OCS units, assuming 300x300 OCS variants are used to support bidirectional links in TPU clusters.

Part 2: Scale-Out

TPUs have quite small scale-out bandwidth - just 100G per TPUv7 or TPUv8. Now consider a hypothetical scale-out cluster made up of 10 of these 9,216-TPU ICI pods (for a total of ~92K TPUs). The aggregate scale-out bandwidth would be 9.2 million Gbps per cluster, or 920 Tbps per pod. Within each pod, Google uses Tomahawk 3 12.8T switches and Tomahawk 4 25.6T switches with 200G-port configuration at the leaf, spine, and core layers. Since it’s all-to-all connected, the pod’s full 920 Tbps bandwidth will be carried all the way up to the core layer.

On top of the core layer (super core) sit the OCS switches, which are used to interconnect the 10 pods. The advantage of OCS is that it can carry traffic with higher bandwidth and provides lower latency, and it benefits from cross-pod traffic patterns that are relatively stable and predictable.

Here’s the math: 9.2 million Gbps of aggregate bandwidth corresponds to 46K 200G ports that are routed through the OCS layer. Assuming 288 usable ports per side, at least 160 300x300 OCS units (46K/ 288) would be needed to interconnect all the spine switches. By comparison, if you use Tomahawk 4 25.6T switches at super core, each switch would provide only 128 ports (compared to 288 for OCS), so building the layer would require more than twice as many switches. This illustrates why OCS is more efficient in this use case.

Overall, 160 OCS switches support a cluster of ~92K TPUs, implying an attach ratio of 575:1. Even with some backup capacity added to improve routing flexibility and resilience, the attach ratio should still remain at least 500:1. Applying this to our estimate of 2.5-3 million TPU installations in 2026, we arrive at demand for ~5-6K OCS units. Combining scale-up and scale-out, our bottom-up approach suggests Google‘s internal OCS demand for 2026 at around 18-22K units.

That implies the market estimate of 18K Google OCS units in 2026 is conservative. In my view, actual deployment is more likely to exceed that estimate than fall short of it.

Part 3: Scale-Across

Google has not used OCS for its scale-across networking. Thus, for scale-across, I am using Microsoft as the example, specifically its Fairwater data centers in Atlanta. There, Microsoft uses a rail-only backend network architecture with 512-radix Spectrum-5 51.2T switches at the leaf and spine layers in a two-layer network. On top of that sits OCS to scale across links and connect to other data centers.

The site has 350MW of total power, which corresponds to ~150K GB200 GPUs based on rack power levels and infrastructure overhead. Under the rail-only architecture, Google splits each compute tray of four GB200 GPUs (800G scale-out each) into 32 100G links and scales through 32 separate planes. Using the formula 2 x (K/2)^L, where K is the number of effective ports and L is the number of layers, the total number of compute trays that can be connected using a 2-layer network is 2 x (512 radix / 2) ^ 2 = 131K. Since each compute tray contains 4 GPUs, the network can connect up to 524K GPUs, which is more than enough to cover the site’s actual GPU count of about 150K.

With this network, the full 150K x 800G of scale-out bandwidth is carried to the spine layer across 32 planes, with each link running at 100G. From there, the system combines every eight links onto a single fiber using DWDM. That results in a total of 150K 800G data streams to be sent to the OCS.

At the core OCS layer, the network is oversubscribed, so only a portion of the total traffic needs to be sent to other sites. Although the exact ratio is not known. Meta, for example, has used a 3:1 oversubscription ratio. For this exercise, let us assume Microsoft uses a 5:1 ratio. On that basis, a total of 30K 800G links would need to be routed. Using 144 x 144 OCS, that implies an OCS demand of ~200 units to route traffic from Atlanta to the other data centers such as Fairwater-I in Wisconsin.

With 150K GPUs and 200 OCS, the attach ratio is 750:1.

Part 4: Total Cost of Ownership (TCO)

Google’s ICI network uses one optical module per surface in the 4 x 4 x 4 cube, along with 48 OCS across the full ICI domain of 9,216 TPUs. The remaining networking-related spend is mainly for DAC connections between TPUs within the same rack, which is relatively low, so I am excluding it from this calculation. Based on the table below, I estimate the total cost of major networking equipment at $18 million per ICI domain, or $1,923 per TPU. The networking power per TPU is 28W.

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In this article, you will learn:

• The use cases of OCS

• The workload types suited for OCS

• The 2 major OCS platforms so far

• The challenges of scaling OCS port counts further

• The 4 main types of OCS, their pros and cons, and the major vendors

• The key components of OCS and BOM analysis

• OCS shipment volumes from 2024 to 2026

• Current selling prices for 128x128 and 300x300 OCS

• The main OCS producers: Lumentum, Coherent, and Huawei

• The main OCS customers: Google and others

Enjoy!

Part 1: OCS Basics

Part 1.1 Use cases and suitable workloads

There are three main types of use cases for OCS. 1) Scale-up: Google uses OCS to interconnect multiple racks within its ICI pods. For example, OCS interconnects 9,216 accelerators in TPUv7 clusters, enabling what is currently the world’s largest scale-up domain, compared with just 72 GPUs in Nvidia’s current-generation GB200/300 NVL72 systems. 2) Scale-out: OCS is typically deployed in the uppermost layers of the network (such as the core layer or super core layer), where there is much less demand for complex workloads such as packet splitting, packet aggregation, and packet encryption. 3) Scale-across: OCS can be used to support large-volume data transfers between data centers. In this role, its high bandwidth per port and longer upgrade cycle make it an attractive option.

In terms of type of workloads, OCS has been mainly used for training. This is because it currently has limitations in switching speed (the speed of reconfiguring signal travel path through the switch) - OCS typically reconfigures at the millisecond level, whereas electronic packet switches (EPS) operate at the microsecond level. Training traffic patterns are generally more predictable and data paths do not change often, helping offset OCS’s switching speed drawbacks. In practice, model trainers only need to reconfigure data paths after a period of time - whether that is 30 minutes, 1 hour, or even several days - and during that time, the input/ output ports mapping remains unchanged. Only after that training job phase is complete do you reconfigure the OCS into a different topology.

This is broadly how Google has used OCS in many of its deployments so far: as long as the input-output mapping does not need to change frequently, OCS works well. In return, you capture a lot of the benefits OCS offers, including ~40% reduction in networking total cost of ownership (TCO).

For more details about Google’s TPU clusters, check out our previous article from this month:

Part 1.2 Port Configurations

Before 2026, the main OCS configurations on the market were 128x128, 136x136, and 144x144, meaning 128 (or 136, or 144) input ports + 128 (or 136, or 144) output ports. All these configurations were fundamentally derived from the same underlying 176x176 platform. In practice, some ports were typically always left unused because of yield margin (not every theoretical port becomes good enough for production use) and spare capacity considerations. As a result, we’ve seen a lot of 128x128 in early stages while much more 144x144 later as yields improved.

Starting in 2026, however, most shipments are expected to move into the 300x300 range, which are based on the 384x384 platform. Developing a 300x300 OCS is quite challenging. As port counts increase, manufacturing becomes significantly more difficult as the system must support and precisely manage a few more hundred optical paths simultaneously. One of the biggest bottlenecks today is the 2D collimator process, which aligns several hundred fibers into the OCS within a dense physical footprint.

Beyond 384x384, the next generation is expected to be 576x576 configuration, where maintaining low signal loss at connection points becomes exponentially more difficult. The industry doesn’t expect such a product to be ready before 2H27. Additionally, some people think 576x576 may be the practical ceiling for OCS ports. That said, the technology continues to evolve, and further scaling beyond this level cannot be ruled out yet.

Part 1.3 OCS Advantages

OCS is not cheap. A 128x128 OCS now sells at around $30-40K, while a 300x300 OCS is priced as high as $150K for the sampling stage. This is significantly more expensive than an EPS - a blackbox 51.2T Tomahawk 5 switch sells at ~$30K and an 102.4T Tomahawk 6 switch sells at ~$40K.

So why are customers still buying OCS despite the much higher upfront cost?

One key advantage of OCS is its ability to support higher bandwidth as it is largely speed agnostic. OCS switches light paths rather than electronically processing the signal, so the underlying switching mechanism remains essentially the same whether the link is carrying 400G, 800G, 1.6T, or even higher data rates. By contrast, in an EPS system, supporting higher-bandwidth transmission usually requires a new generation of switch silicon with greater processing capability. As a result, the same OCS can often continue to be used as networks migrate to 1.6T or 3.2T links over time, whereas EPS needs to be upgraded to a new switch generation.

Secondly, OCS provides lower power consumption and offers lower forwarding latency. Because the signal remains in the optical domain from end to end, OCS avoids the optical-to-electrical and electrical-to-optical conversions that take place at EPS. This can reduce power consumption by ~30% and latency by ~30%. Note that OCS does have higher reconfiguration latency when changing paths, but when the traffic pattern is fixed, the signal can traverse the switch much more quickly. Overall, this combination of lower power consumption and lower latency is the main reason OCS can help reduce total network TCO.

Part 2: OCS Roadmaps

The two main types of OCS so far are MEMS-based OCS and LCoS-based OCS.

Part 2.1 MEMS-based OCS

MEMS-based OCS uses tiny movable mirrors, built with micro-electromechanical systems, to steer light beams from one input port to a selected output port. They’re currently the most widely used OCS method.

MEMS OCS has several advantages over LCoS-based variants: 1) relatively faster switching speed, typically at the millisecond level, versus dozens of milliseconds for LCoS OCS; 2) relatively lower insertion loss; and 3) easier product development, and has reached volume production much earlier than any other types.

Companies providing MEMS OCS include Google (internal design), Lumentum (U.S.), and Calient (Taiwan).

Part 2.2 LCoS-based OCS

Liquid-Crystal (LCoS)-based OCS applies different voltage levels to a silicon backplane coated with liquid crystal to steer the light path. Its main advantage is longer operating lifespan - an LCoS OCS can last maybe 10 years, compared with roughly 3 years for a MEMS-based OCS, whose mechanical components are more prone to wear and failure. This longer lifespan can materially improve TCO. For example, both types’ 300×300 systems have similar upfront cost, but a 10-year lifespan gives the LCoS variant a 70% reduction in annual ownership cost.

The main disadvantage of LCoS is its relatively high switching latency, at tens of milliseconds. This makes it not suitable for scenarios that require very dynamic reconfiguration.

Companies providing LCoS OCS include Coherent and Huawei.

In addition to MEMS and liquid crystals, there are two other types of OCS that are still in development, but they could play important roles in the future.

Part 2.3 Waveguide-based OCS

Waveguide-based OCS routes light through integrated waveguides fabricated on a photonic chip, with switching controlled by on-chip elements such as Mach-Zehnder interferometers (MZIs) or ring resonators. Unlike other OCS methods that rely on assembling discrete optical components, this architecture is built using integrated silicon photonics manufacturing processes - it’s just like the silicon photonics modules vs. the traditional EML/VCSEL-based modules in the transceiver industry!

One main advantage of waveguide-based OCS is its fast switching speed, at the microsecond level, compared with the millisecond-level switching of MEMS- or LCoS-based OCS. This switching speed is comparable to EPS’s. As such, waveguide OCS is the most suitable OCS type for reasoning workloads that require highly dynamic reconfiguration.

However, several bottlenecks still need to be resolved before waveguide-based OCS can see meaningful adoption. One, insertion loss is still high, roughly 2x that of MEMS- or LCoS-based OCS. The current workaround is to use external SOA amplifiers to offset the loss, but placing the amplifier externally creates manufacturing and yield challenges, and thus higher production costs - currently waveguide-based OCS solutions cost more than 3x of MEMS/ LCoS ones. The more promising long-term solution is to integrate the amplifiers directly with the silicon of the OCS on InP substrates, but this type of heterogeneous integration is highly complex and still requires several years to mature.

Two, scaling the number of ports appears more challenging for waveguide-OCS, as increasing the port count for this type of solution introduces more crosstalk among the switching elements.. The current generation of wave-guide OCS remains limited to 32x32 configuration. Overall, the industry does not expect volume production of this architecture before 2H27.

Part 2.4 Piezoelectric ceramic-based OCS

Piezoelectric-ceramic-based OCS: uses piezoelectric ceramic actuators to precisely move and align optical components, thereby adjusting optical paths. Its key advantage is very low insertion loss at around 1 dB, compared with ~3 dB for MEMS- and LCoS-based OCS and ~6 dB for the waveguide-based variant. However, it is currently very expensive to manufacture, also costing more than 3x that of MEMS or LCoS. As a result, broad adoption of piezo OCS is also some distance away.

Companies providing Piezo-based OCS include Polatis.

Part 3: Key Components of OCS

Part 3.1 MEMS-based OCS key components and BOM

• MEMS chips: are the control core of the MEMS-based OCS system - they drive the micromirrors to steer light toward the desired output port. In a 176x176 platform, the system contains 176 individual micromirrors, with a total cost of close to $6,000 in the early stages and over $4,000 now as production volume scales. Over time, the supply chain aims to reduce this cost further to ~$2,000.

  For the 384x384 platform, however, cost is pretty high - well above $10,000 - because production volumes are still low, and each 384x384 OCS requires two such systems.

  The key supplier of MEMS systems for Google’s OCS has been Swedish company Silex, which accounts for ~70% of the volume. We heard Texas Instruments (TXN) could be the second source. Chinese company Sai MicroElectronics (300456.CH) owns 45% equity in Silex.

• Calibration system: is used to ensure that light does not deviate from its intended transmission path. It typically includes the transmitting module, receiving module, and camera module. For Google’s OCS, the cost of the system is around $4,000.

• 2D collimator arrays: are the optical assemblies that ensure the input and output fibers align precisely with the ports and internal optical path of the OCS, allowing light to enter and exit the system accurately. They are critical to the overall performance and reliability of the switch. A collimator array in MEMS OCS can be further divided into two components: the fiber array and the lens array. The fiber array provides the mechanical alignment between the fibers and the ports, while the lens array is responsible for the optical collimation and alignment at the conjunction points.

  For a 176x176 MEMS platform, the fiber array typically costs a little over $1,000, while the lens array costs several hundred dollars, bringing the total cost of the collimator system to close to $2,000. For the 384x384 platform, the fiber array costs slightly over $2,000, and the lens array is also a few hundred dollars (but more expensive than the ones in 176x176), making the total cost close to $3,000.

  The key suppliers for Google are Coherent, Molex, and Fiberguide for the fiber arrays, and Ingeneric for the lens arrays. We heard that T&S and Corning may also be involved, but are unsure about their exact level of involvement.

• 2D MEMS array: are used to control the optical path inside the OCS, composed of micromirrors. The cost of the system is usually around $3-400. For Google’s OCS, the supplier of these 2D MEMS arrays is Focused Photonics (300203.CH).

• Dichroic beamsplitters: are used to separate light of different wavelengths, by allowing certain wavelengths to pass while blocking others. In OCS, they can be used to separate testing and monitoring signals from data-carrying signals. The cost of dichroic beamsplitters in Google’s OCS systems is also a few hundred dollars.

Overall, the BOM cost of a 176x176 MEMS-based OCS is about $13K - MEMS chip accounts for ~35% of the BOM, followed by calibration system at 30%, 2D collimation array at 15%, 2D MEMS array plus dichroic beamsplitters at 5-10% and other components at 10%. After adding ~10% for manufacturing cost, the total production cost comes to ~$14K. At the current selling price of over $30K, this implies a GPM of ~55%.

Part 3.2 LCoS-based OCS key components and BOM

The first LCoS-based OCS products are expected to ship in the 384x384 platform, so the discussion below is based primarily on that configuration.

• Liquid crystal: In an LCoS-based OCS, the liquid crystal is the part that actually controls where the light goes. When voltage is applied, the liquid crystal changes how the light experiences phase, polarization, or direction, and that lets the switch steer the beam toward a chosen output path. For the 384x384 platform, the cost of liquid crystal is close to $20K now.

• 2D collimator array: has the same function as those in a MEMS-based OCS. However, in an LCoS-based OCS, the total cost of the 2D collimator array system is higher, currently ~$12-14K for the 384x384 platform. This is because the LCoS architecture requires tighter beam control and thus more precise alignment of the light and the switch.

• Beam displacer: is used to split the incoming light into two beams based on polarization, allowing the LCoS OCS to process and transmit each beam separately before recombining them at the final output. This process is important because an LCoS switch works best when the light is in a known polarization state, but the incoming light usually has random polarization. By separating the signal into two known polarization components, the system can control each one much more accurately. The cost of beam displacers in a 384x384 platform is ~$10K.

• Birefringent wedge: IS used to steer the beam/ light into a selected output port rather than allowing it to pass straight through. This serves a role similar to the 2D MEMS array in a MEMS-based OCS. The cost of the birefringent wedges in a 384x384 platform is ~$2-3K.

Overall, the BOM cost of a 384x384 LCoS-based OCS is close to $50K - liquid crystal accounts for ~35% of the BOM, followed by 2D collimation array at 30%, the beam displacer at 20%, optical wedges at 5%, and other components at 10%. After adding ~10% for manufacturing cost, the total production cost comes to ~$50-60K. At a current sampling-stage selling price of ~$150K, this implies a GPM of slightly above 60%.

Part 4: OCS Volume and Pricing

Part 4.1 Volume

In 2024, Google was the sole customer of OCS, deploying ~6-7K units of OCS for its TPU clusters. All of them are internally designed modules based on the MEMS system.

In 2025, Google remained the dominant buyer, deploying ~12-15K units of OCS. Most of these were 128x128 or 144x144 systems, and all were still MEMS-based.

In 2026, total OCS demand is expected to exceed 20K units for the whole market. Of this, Google will account for ~18K units, with the remaining few thousand from other hyperscalers. Within Google’s deployment, most of the volume is still going to come from internally designed MEMS OCS systems. However, roughly 5-6K units will be externally procured, mainly from Coherent (LCoS-based OCS) and Lumentum (MEMS-based OCS). We will discuss more details in the customer section.

Part 4.2 Price

When 128x128 OCS first entered the market, pricing was around $50-60K, but it has since declined to roughly $30-40K. A more meaningful benchmark is the price per port, which is typically the basis used for OCS pricing. At $50-60K total pricing, the per port price is $400-450, while at $30-40K, the per port price falls to $250-300. Google’s internal goal is to reduce the price to $250 per port or below over time.

300x300 OCS systems began sampling at the end of 2025, with an initial selling price of ~$150K and a production cost of ~$60K (~60% GPM). On a per-port basis, this translates to pricing of ~$500/ port. As volumes begin to ramp, per-port pricing is expected to decline to at least $350-400, implying a total system price of ~$100-120K, while production cost falls to $50K (~55% GPM). Further reduction in per port prices will likely require engineering improvements and larger-scale volume ramp. Manufacturing complexity rises significantly at this generation, so it may not be straightforward for the 384x384 platform to reach the per-port economics of the 176×176 platform very quickly.

Part 5 OCS Producers

Lumentum (LITE): The company primarily produces MEMS-based OCS, although it also has some capabilities in LCoS-based OCS. Its main commercial products are 300x300 OCS for Google (mainly) and Oracle. It also has its 64×64 OCS samples sent to Microsoft and Nvidia for testing. The company’s OCS production base is in Thailand, with volume ramp expected in 4Q26. At present, demand is clearly outstripping supply, and the company believes it can sell as many as it can produce this year. The company shared at this year’s OFC that it is targeting a $1 billion OCS run rate in 2027.

Coherent (COHR): Google and Oracle are also the company’s main OCS customers. Coherent is expected to ship ~3,000 LCoS-based OCS units to Google in 2026, with volume ramp beginning in 1H26 (earlier than Lumentum). Overall, the company said that they have received >$300 million of orders from Google and Oracle. At $100K ASP, this would translate to >3,000 units, which is consistent with our previous projections.

Coherent’s capacity target is 1,000 units per month, a level it should be able to reach by 2H26. Beyond Google and Oracle, the company has also provided samples to Meta, Microsoft, Amazon, and Nvidia for testing. On its most recent earnings call, The company stated that it is currently engaged with 10 OCS customers.

Huawei: The company has strong in-house capabilities to develop and produce MEMS-based OCS, which have been deployed in its CloudMatrix 384 clusters.

Other notable vendors of OCS include Polatis for piezoelectric ceramic-based OCS and iPronics for waveguide-based OCS, as highlighted earlier. However, neither company has received meaningful volume production orders yet.

In the paid section below, we will discuss the main buyers of OCS and their deployment status and strategy, including Google, Microsoft, Oracle, Meta, and Nvidia. We will also look specifically at Google’s internal development so far and external procurement starting in 2026.

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Core thesis: TPU is not broadly superior to GPU. It is economically superior when workload regularity, deployment scale, and software control are high enough for system-level optimization to matter.

Today, we take a comprehensive look at Google’s TPU platform and its growing role in AI infrastructure. Over the course of this article, you will gain a clear understanding of the following topics:

• The history and evolution of Google TPUs

• What a TPU is and how it works

• Google’s commercial progress and TPU deployment momentum

• TPU–GPU differences in architecture and system design

• TPU–GPU comparisons in performance and utilization

• TPU–GPU comparisons in cost-performance and full-data-center TCO

• What TPUs mean for the competitive landscape of AI infrastructure

Section 1: A Brief History of the TPU

Google introduced the Tensor Processing Unit (TPU) in 2016 as an internal ASIC optimized for neural-network inference. Its early use cases included Search, Ads, and YouTube recommendation workloads, where dense matrix operations and predictable inference patterns made specialized hardware more efficient than general-purpose CPUs or GPUs.

Over time, TPU evolved well beyond that initial role. The platform moved from inference-only hardware to training-capable accelerators, then to pod-scale systems, and eventually to a broader cloud platform that now serves both internal workloads and external customers. In strategic terms, TPU’s evolution can be read as a sequence of shifts: from internal acceleration, to cloud differentiation, and increasingly to external commercialization.

The broad progression is clear. TPU v1 was inference-only and built around low-precision matrix operations. TPU v2 and v3 added training support and high-bandwidth memory. TPU v4 marked the emergence of pod-scale deployment and serious competition with NVIDIA in large training environments. Later generations introduced clearer segmentation across training and inference use cases, alongside higher performance-per-watt and stronger large-model efficiency. Looking ahead, market expectations point to a continued separation between high-end training systems and more cost-optimized inference-oriented SKUs, although the exact future product roadmap should be treated with caution unless explicitly confirmed by Google.

TPU Generations

Section 2: TPU Design and Features

Google’s TPU architecture is fundamentally designed around system-level efficiency rather than single-chip peak performance, reflecting a philosophy that diverges sharply from general-purpose GPU design.

• Compute Core: Systolic Arrays and Dataflow Optimization

  At the heart of each TPU lies a large-scale systolic array (Matrix Multiply Unit, MXU), purpose-built for dense linear algebra operations. Unlike traditional SIMD/SIMT architectures, TPUs adopt a dataflow-driven execution model (often weight-stationary), minimizing data movement and maximizing reuse within the array. This approach significantly improves efficiency for transformer-based workloads, where matrix multiplications dominate compute cycles.

• Interconnect: Scaling as a First-Class Design Goal

  TPUs are architected as distributed systems from the ground up. Through a custom Inter-Chip Interconnect (ICI) and integration with optical circuit switching (OCS), TPU pods can scale to thousands of chips with high-bandwidth, low-latency communication. This enables tightly synchronized distributed training and high-throughput inference, effectively treating the pod - not the chip - as the primary unit of computation.

• Memory Architecture: Bandwidth as the Bottleneck

  Memory architecture is equally central to TPU design. In modern AI workloads, the bottleneck is often not peak compute, but the ability to keep compute units continuously fed with data. TPUs address this not simply through high-bandwidth memory, but through a broader dataflow-oriented architecture that reduces data movement and improves bandwidth utilization. As a result, TPUs can be especially efficient on regular, matrix-heavy workloads such as large language model training and inference.

• Hardware–Software Co-Design

  These hardware decisions are inseparable from the software stack. TPU performance depends heavily on Google’s broader ecosystem, particularly XLA, JAX, and TensorFlow. Because optimization is compiler-led, Google can analyze larger portions of the computation graph before execution and apply global transformations that are difficult to achieve in a more general-purpose runtime model. This includes fusing multiple operations, minimizing intermediate memory writes, controlling tensor layout, and mapping workloads more directly onto systolic arrays and on-chip memory. In practice, this hardware-software co-design is one of the main reasons TPU systems can achieve high realized utilization at scale, especially on regular, matrix-dominated AI workloads.

• Efficiency vs Flexibility Trade-off

  The trade-off, however, is clear. TPU architecture delivers strong performance-per-watt and attractive cost efficiency in large, well-optimized deployments, but it is less flexible than GPUs for irregular, dynamic, or rapidly changing workloads. Its advantages are most pronounced when workloads are highly structured, models are large and relatively stable, and execution can be optimized end to end through the compiler.

In summary, TPUs should be understood not as isolated chips, but as tightly integrated systems. Their true advantage emerges not from peak FLOPs on a single device, but from co-optimizing compute, memory, interconnect, and software across thousands of chips, enabling Google to deliver AI at hyperscale with superior efficiency and economics.

Section 3: Commercialization

TPU’s commercial significance has increased because its customer base is no longer limited to Google itself. What was once predominantly internal infrastructure is increasingly becoming a hybrid platform serving internal products, Google Cloud customers, and a growing set of strategic external partners. That shift matters because it turns TPU from a cost-saving internal asset into a platform that can also generate cloud revenue and strengthen Google’s position in the broader AI infrastructure stack.

Shipments and Forecasts

TPU shipment volumes have scaled rapidly, with generation transitions occurring at a very fast pace. At this stage, growth appears to be constrained less by end-demand than by supply-side bottlenecks, particularly advanced packaging capacity such as CoWoS.

Customer Mix

Google’s TPU deployment is increasingly shaped by a hybrid consumption model, spanning internal workloads, cloud customers, and a fast-growing set of strategic external partners. What was once a predominantly internal infrastructure has evolved into a commercialized AI platform with rising external demand.

Internal Google: A large share of TPU capacity is still dedicated to Google’s own products and services, including Search, YouTube, Ads, and Gemini. Industry estimates suggest that in 2025, internal usage accounted for roughly 80% of total TPU shipments, highlighting that TPU was still primarily an internal infrastructure asset. By 2026, internal shipments are expected to remain stable, but the share of total volume declines sharply to around 50% as external-facing demand accelerates. Internal usage therefore remains strategically important, but it is no longer the sole driver of the TPU scale.

Google Cloud Platform: TPUs are becoming a more important differentiator for GCP, particularly in large-scale AI workloads where price-performance matters. Our channel work suggests GCP-related TPU increase from about 15% in 2025 to roughly 30% of total shipments in 2026. This suggests that Google Cloud is moving from a secondary channel to a major source of TPU commercialization. The customer base includes both enterprise workloads and AI-native model developers that access TPUs through Google-hosted infrastructure. Importantly, this category also includes large strategic customers that obtain TPU capacity through a rental model rather than direct ownership, such as Meta and Anthropic. As a result, part of what appears as GCP consumption is in fact strategic external demand delivered through Google’s cloud channel.

External Strategic Customers: We define external sales as the direct purchase of TPUs for deployment in customer-owned data centers. This remains a small channel in 2025, at around 5% of total shipments, but scales rapidly to nearly 20% of total volume in 2026, according to industry estimates. The sharp increase suggests that TPU adoption is beginning to move beyond internal deployment and cloud rental toward more strategic, customer-owned infrastructure. In many cases, large customers appear to follow a progression: first renting or testing TPUs through cloud access, then moving toward direct deployment once performance and economics are validated.

Large External Customer

• Anthropic

  The partnership between Anthropic and Google Cloud is a structurally complex AI infrastructure agreement, combining direct hardware procurement with long-term cloud capacity commitments. Anthropic plans to deploy up to ~1 million TPUs, with a significant portion sourced as rack-level systems directly from Broadcom, alongside large-scale consumption through Google Cloud. The relationship is structured as a hybrid model: Anthropic secures baseline capacity and control via owned infrastructure, while leveraging GCP for elastic scaling, orchestration, and managed services.

  Recent disclosures from Broadcom indicate that direct hardware orders have expanded beyond initial expectations - from ~$10B to ~$21B, implying a substantial increase in Anthropic-owned TPU capacity and signaling a strategic shift toward partial vertical integration of compute. At the same time, Google captures the majority of economic value through cloud services, with an estimated ~$42B+ in committed GCP spend (RPO) tied to TPU usage. This dual structure effectively transforms the partnership into a long-term reservation of AI manufacturing capacity, where Anthropic secures supply in a constrained market, and Google locks in demand to justify continued infrastructure buildout.

Anthropic TPU Adoption Roadmap

• Meta

  The commercial rationale behind this cooperation is straightforward. Meta and Anthropic share certain similarities at the model level, and Meta’s Llama roadmap, like Google’s Gemini, is increasingly associated with architectures that benefit from large-scale, highly efficient AI accelerators, including MoE-like design approaches. Google has already demonstrated that Gemini can run effectively on TPUs, with clear economic benefits in both training and inference. Against that backdrop, Meta wants to test whether Google’s TPU platform can deliver better value than NVIDIA GPUs for deploying and scaling Llama. That expected improvement in performance economics is the core business driver behind the partnership. Meta’s cooperation with Google appears to follow a two-phase approach.

  Phase 1: TPU rental and technical evaluation in 2026.
  Meta is expected to rent Google TPUs in 2026 to test Llama models on the platform. The purpose of this phase is to evaluate how effectively Llama can be adapted to TPUs, including both inference and training workloads. In practical terms, Meta wants to assess whether TPUs can meet the performance, scalability, and efficiency requirements of the Llama family before making a larger infrastructure commitment.

  Phase 2: Potential TPU procurement for Meta-owned data centers in 2027.
  If the testing phase shows that TPUs can support Llama training and inference at the required level, Meta could move to a second stage in 2027 by purchasing TPUs from Google and deploying them in its own data centers. This would mark a shift from short-term evaluation to long-term infrastructure adoption.

• Apple

  Apple has emerged as a meaningful external buyer of Google’s TPUs, purchasing roughly 100,000 TPU v5p chips in 2024. Demand is expected to accelerate further in 2025, with Apple’s procurement to double to around 200,000 units. This expansion reflects a broader industry shift also seen at Meta, OpenAI, xAI, and Anthropic, as leading AI developers seek to reduce reliance on NVIDIA’s expensive hardware and tightly controlled software ecosystem. Apple’s sustained appetite for Google TPUs has made it one of the most important third-party drivers of Google’s external TPU shipments, underscoring the growing commercial relevance of TPUs beyond Google’s own internal workloads.

• OpenAI

  OpenAI has begun renting Google TPUs through Google Cloud, but its usage appears to remain at an early testing stage rather than a broad production deployment. At this point, TPUs seem to serve more as a source of commercial leverage in OpenAI’s negotiations with NVIDIA, helping the company push for better GPU pricing, rather than as a core compute platform adopted at scale. More fundamentally, Google’s TPU architecture does not appear to be an ideal fit for OpenAI’s model stack, which likely limits the probability of TPU becoming a major part of OpenAI’s long-term infrastructure strategy.

• Others: There is no reliable public evidence so far that Microsoft or xAI are Google TPU customers. In Microsoft’s case, the public narrative remains centered on its in-house Maia accelerator strategy, while xAI continues to be associated primarily with large-scale NVIDIA GPU deployments.

Pricing

Google does not publicly disclose a standard standalone purchase price for TPUs. In practice, TPU economics are more visible through Google Cloud pricing and through directional industry checks than through a public list price. That is an important distinction: cloud pricing, transfer pricing, and end-customer economics are not the same thing, and they should not be treated as interchangeable.

Based on our channel checks, indicative TPU chip pricing in early 2026 - referring to the price charged to Google rather than the price paid by end customers - is as follows. Newer generations are not necessarily more expensive, as pricing appears to be driven more by performance profile and workload positioning than by generation alone.

Profit Margin

Notably, Google appears less focused on maximizing standalone chip margins than Nvidia. Google’s gross margins are estimated at ~20-30% when selling TPU to external customers, with profits shared by suppliers. In contrast, Nvidia has a very stable 75% gross margin thanks to its vertical integration of chip design, software and system

Indicative TPU System Value Capture Structure

Percentages are illustrative estimates of system cost and are intended for conceptual analysis only. They are not based on company-disclosed cost breakdowns.

Section 3: TPU vs GPU

Design

At a high level, both TPUs and GPUs accelerate machine learning workloads. In practice, they are built on very different design assumptions. GPUs prioritize flexibility and broad programmability; TPUs prioritize efficiency and system-level optimization for large-scale AI.

As AI shifts from model development to large-scale deployment, that distinction matters more. The competition is not just between two chips, but between two ways of organizing compute, memory, scaling, and software.

• Compute: Flexibility vs. Structured Execution

  GPUs are built around a SIMT model, in which many threads execute in parallel under dynamic scheduling. This makes them highly versatile across graphics, scientific computing, and AI. But that flexibility creates overhead: irregular control flow, thread divergence, and scheduling complexity can reduce efficiency on structured workloads such as large matrix multiplications.

  TPUs take the opposite approach. They are built around systolic arrays, where data moves through compute units in a predictable pipeline. Execution is organized as dataflow rather than thread scheduling, allowing higher utilization on the dense, repetitive tensor operations that dominate modern AI.

Source: The Savvy Canary

• Memory: Bandwidth Matters More Than Raw Compute

  In modern AI systems, performance is often constrained less by peak compute than by data movement. GPUs address this with a flexible memory hierarchy that includes HBM, caches, registers, and shared memory. This makes them highly adaptable across many workload types, but it also means efficiency depends heavily on access patterns, kernel design, and how often data must be written back to and read from memory.

  TPUs use a more explicit bandwidth-first model. Rather than relying as heavily on dynamic cache behavior, TPU memory movement is planned more directly by the compiler, with HBM tightly coupled to compute and dataflow organized around systolic arrays. The goal is to minimize unnecessary movement, improve locality, and keep matrix units continuously fed with data. Put simply, GPU memory systems are designed to handle many kinds of workloads well, while TPU memory systems are designed to move data in the fewest possible steps for highly structured AI computation.

• Scaling: Connected Devices vs. Designed Systems

  The contrast becomes clearer at cluster scale, but it is best understood as a difference in fabric design rather than a simple scale-up versus scale-out divide. In NVIDIA systems, NVLink/NVSwitch serves as the high-bandwidth fabric for tightly coupling GPUs within a node or rack, while InfiniBand or Ethernet connects those systems across larger clusters. This gives GPU infrastructure strong modularity and broad deployment flexibility, but cluster performance depends heavily on how well software manages communication overhead and distributed execution.

  Google TPU systems follow a similar two-level logic, but with tighter integration at the pod level. ICI acts as the high-bandwidth interconnect within a TPU pod, while larger-scale expansion across pods depends on Google’s broader data center network and optical switching. The practical difference is not that GPUs are “assembled” and TPUs are “designed,” but that TPU pods are more tightly co-designed as an integrated system from the start, with communication and topology optimized around a narrower class of large-scale AI workloads.

• Software: Ecosystem Breadth vs. Hardware-Software Co-Design

  NVIDIA’s biggest advantage is not just hardware, but software. CUDA, combined with PyTorch and a broad tooling ecosystem, gives developers a mature platform with fine-grained control over kernels, memory behavior, and execution. This has been one of the main reasons GPUs became the default platform for AI development.

  TPU software works differently. It relies on a more tightly integrated stack centered on XLA, JAX, and TensorFlow, where developers more often describe computation at a higher level and the compiler takes a larger role in optimization. Instead of depending as heavily on programmer-directed tuning, the TPU stack leans on the compiler to optimize the full computation graph - fusing operations, choosing tensor layouts, reducing data movement, and planning execution ahead of time. In simple terms, GPU performance is often tuned more directly by the programmer, while TPU performance depends more heavily on what the compiler can optimize automatically. That approach can deliver very high efficiency on structured workloads, but within a narrower software ecosystem.

• Performance: Peak Throughput vs. Realized Utilization

  These design choices lead to different performance profiles. GPUs are often optimized for peak single-device performance and benchmark leadership. In production, however, realized utilization typically falls meaningfully below theoretical limits because of memory bottlenecks, synchronization overhead, communication costs, and workload variability. A commonly cited rule of thumb for large-scale GPU training is utilization around 30%, although well-optimized clusters can achieve materially higher levels in practice.

  TPUs, by contrast, are optimized less for peak headline numbers than for sustained throughput across tightly integrated systems. Their advantage is often not higher theoretical performance per chip, but more predictable and efficient utilization at scale, especially on structured, compiler-friendly workloads. Some industry estimates place TPU utilization at roughly 40% in favorable settings, though this should be understood as a scenario-dependent estimate rather than a universal benchmark. In production environments - where cost per query, training efficiency, and energy use matter more than peak FLOPs - that distinction can be critical.

• The Core Trade-off

  At its core, the TPU-GPU divide is a trade-off between flexibility and efficiency.

  GPUs offer a broader ecosystem, greater programmability, and stronger support for diverse or fast-changing workloads. TPUs offer tighter hardware-software integration, better scaling characteristics, and higher efficiency on stable, highly structured AI workloads.

  Neither is universally superior. GPUs remain the default where iteration speed, workload diversity, and ecosystem compatibility matter most. TPUs are strongest where workloads are predictable, deployment is hyperscale, and system efficiency matters more than generality.

The TPU vs. GPU debate is often framed as a chip competition. More fundamentally, it is a competition between architectural philosophies.NVIDIA has built the dominant general-purpose AI compute platform. Google has built a more specialized system optimized for delivering AI efficiently at scale.As the industry shifts from training models to serving them economically, the key distinction will increasingly be not peak performance, but realized performance; not flexibility alone, but efficiency at scale.

Comparison between TPU and GPU

Hardware Specs

The framework we use is to evaluate the hardware across three dimensions: compute performance, memory subsystem, and interconnect / cluster architecture. Within compute, it is also important to distinguish between peak compute and effective compute. Peak compute refers to the theoretical maximum throughput under ideal conditions, while effective compute reflects the portion of that performance that can actually be converted into useful training or inference work after accounting for memory constraints, communication overhead, software efficiency, and utilization at scale.

• Compute performance: The most relevant comparison today is increasingly centered on FP8 throughput, which has become the primary battleground for leading-edge AI accelerators. Google’s latest TPU v7 (Ironwood) has become much more competitive with NVIDIA’s latest Blackwell generation than in prior cycles. According to Google Cloud’s published specifications, TPU v7 delivers 4,614 TFLOPs of FP8 peak compute per chip. By comparison, NVIDIA positions GB200 at roughly 5,000 TFLOPs of FP8 compute, meaning the gap in raw dense low-precision throughput has narrowed materially. For context, the previous-generation TPU v6 (Trillium) offered 918 TFLOPs of dense FP8 compute, which means TPU v7 represents a major generational step-up and a substantial narrowing of the competitive distance versus NVIDIA’s newest platform. In other words, on a pure peak-FLOPs basis, TPU v7 is no longer clearly outclassed by NVIDIA’s flagship platform; instead, the two are now in the same performance tier.

  That said, comparing AI chips on FP8 performance requires an important distinction between theoretical peak compute and effective compute. In practice, the headline FLOPs figures marketed by vendors such as NVIDIA and AMD often reflect instantaneous peak performance achievable under favorable conditions, sometimes aided by dynamic voltage and frequency scaling, rather than the level of throughput that can be sustained across real production workloads. As a result, theoretical FP8 performance can overstate what users actually realize in large-scale training. For GPUs, actual utilization of advertised FP8 compute - often measured by Model FLOP Utilization (MFU) - is typically much lower, with real-world training workloads often achieving utilization levels around 30%. By contrast, Google’s TPU architecture is generally viewed as more conservative in how performance is specified, meaning its stated compute is often closer to sustainable delivered throughput. This matters because for highly optimized operators, effective compute can diverge materially from theoretical peak. In particular, elite users such as Anthropic have reportedly been able to push TPU utilization to around 40% MFU through deep system-level optimization, allowing TPUs to deliver very strong effective compute economics even when their headline peak FLOPs remain slightly below NVIDIA’s top-end figures. In other words, while NVIDIA may still lead on nominal peak compute, TPU can be more competitive on usable compute than raw spec-sheet comparisons alone would suggest.

• Memory capacity and bandwidth: TPU had historically been at a disadvantage, but that weakness has been substantially reduced in the latest generation. Google states that TPU v7 includes 192 GiB （192 GiB ≈ 206 GB. ） of HBM per chip and 7,380 GB/s of HBM bandwidth, a major step up from prior TPU generations. This means TPU v7 now matches GB200 on memory capacity, as NVIDIA’s Blackwell platform is commonly described with 192GB HBM3E （HBM is the memory category; HBM3E is a newer generation with higher bandwidth and improved efficiency）at the GB200 level. That said, NVIDIA still extends its lead at the upper end with GB300, which raises memory capacity to up to 288GB HBM3E per GPU and bandwidth to roughly 8 TB/s. So on memory, the latest comparison is no longer “TPU far behind GPU”; instead, it is more accurate to say that TPU v7 has reached parity with GB200-class capacity but still trails GB300 at the frontier end of the Blackwell Ultra family.

• Interconnect and cluster scale: Google documents that TPU v7 supports pods of up to 9,216 chips, using a topology built around direct inter-chip links and large-scale pod interconnection. By contrast, NVIDIA’s flagship commercial Blackwell system is typically framed around the GB200 NVL72 or GB300 NVL72 rack-scale configuration, which organizes 72 GPUs into a single NVLink domain. NVIDIA’s NVL72 is extremely powerful and highly optimized, but it is still a much smaller native building block than a full TPU pod. This difference matters because at frontier scale, the bottleneck often shifts from single-chip speed to the efficiency of synchronizing thousands of accelerators. In that environment, TPU’s large native cluster design can translate into stronger effective scaling behavior, particularly for workloads that are communication-heavy or require tightly coordinated distributed execution.

Taken together, the latest-generation comparison is much more balanced than older TPU-versus-GPU narratives suggest. NVIDIA Blackwell still appears stronger in software maturity, commercial ecosystem breadth, and top-end memory in its GB300 configuration. But Google TPU v7 has largely closed the gap in peak compute, substantially narrowed the memory disadvantage, and retains an architectural advantage in pod-scale interconnect and large-cluster efficiency. As a result, the most important conclusion is not simply that NVIDIA leads on peak specs or that TPU is cheaper; rather, it is that TPU is now credible on both peak compute and effective compute, especially in hyperscale environments where delivered utilization and system-level scaling matter more than isolated chip benchmarks.

In the paid section of the article, we will continue to discuss:

• The software and ecosystem difference between TPU and GPU

• What Google has done to catch up in software capabilities and ecosystem

• TCO difference of TPU vs. GPU at peak utilization as well as effective utilization

• Conclusion and main takeaways

Read more

ALAB’s stock price has dropped about 30% since its 5-day peak. I think this could present a good buying opportunity. Below is my summary of the company’s earnings call on Feb 10, 2026, where I’ve highlighted only the most important and meaningful points, along with my own commentary to help put them into context. There’s quite a lot of interesting contents on switches.

This note is free.

Section 1: Financials

• Q4 results

  • Revenue $270.6M, +17% qoq, +92% yoy

  • Exceptionally strong spending commentary from Google & AWS, guiding $400B capex for 2026

  • Market opportunity for our connectivity platform is substantially larger than anticipated

  • Non-GAAP GPM 75.7%, down 0.7 pct, due to higher mix of hardware sales

  • Non-GAAP operating expenses $96 million, up $16M, due to R&D expansion, incl. aiXscale

  • Non-GAAP OPM 40.2%, down 1.5 pct

  • Non-GAAP: SBC, acquisition-related costs and its related income tax effects

  • CFO $95.3 million, cash equivalents and marketable securities of $1.19 billion

• Q1 2026 guidance

  • Revenues $286-$297 million, +6~10% qoq

  • Aries: growth driven by variety AI platforms across scale-up and scale-out

  • Taurus: driven by 400G scale-out

  • non-GAAP GPM 74% with the increased mix of hardware-based solutions

  • non-GAAP operating expenses $112-$118 million

  Comment: Not an aggressive guidance.

• $6.5 billion follow-on warrant with Amazon:

  • 3.3M warrant shares for purchase up to $6.5 billion of switches, signal conditioning, optical

  • As the warrants are achieved, model a noncash hit to gross margins of ~2% a quarter from Q2

  Comment: follow-on warrant with Amazon shows continued commitment from it’s most important client.

Section 2: Products

Aries

• PCIe 6 solutions contributing robust growth, overall portfolio +nearly 70% yoy

  • Driven by increasing deployments of custom AI accelerators

• Industry’s only PCIe 6 DSP retimer solutions in high volume now, expect to maintain lead role

• Very early in PCIe 6 transition cycle

• Add’l customers will launch PCIe 6 capable XPUs throughout 2026, into 2027

• Aries 6 strong as shipping PCIe 6 SCMs for scale-up topologies in high volume

Taurus

• Taurus is strongest performing family in Q4 as new programs ship in volume (both AI & general)

• 2025 revenue + >400% yoy, driven by 400G; continued growth in 2026

• 800G the next catalyst: very closely engaged in qualification process; multiple customers

• We don’t do the whole cable, we do the modules that go inside the cable assemblies

  • Rely on cable partners to deploy at-scale w/ multi vendors support the same opportunity

  Comment: Interesting to see that Taurus is still primarily driven by 400G, while most of the market had already shifted heavily toward 800G in H2 2025. These AECs were supplied to AWS for first-layer scale out of its Teton 2 PD/PDS racks.

Leo

• Leo made progress in CXL memory expansion in 2025

• Partnership with Microsoft: customers (Intel/SAP) to evaluate CXL in Azure M-series virtual machines

• Industry’s first publicly announced deployment; expect initial volume in H2 2026

  Comment: it appears CXL is still not getting too much traction yet.

Switches

• Scorpio-P (scale out)

  • Continued volume ramp at AWS, from both existing & incremental platforms

  • Launched in Q2 2025, Scorpio >15% of total revenue in 2025 (mainly Scorpio-P)

  • Remains the only PCIe 6 switches with significant volume in the market

  • 2026: expect commencing into at least 2 add’l major hyperscalers on their next-gen AI platform (production by end 2026)

  Comment: encouraging to see Scorpio-P expanding to new hyperscalers except for AWS.

• Scorpio-X (scale up):

  • Initial volumes in Q4; expect to incrementally grow revenue 2026H1, transition to high-volume in H2

  • Engaged with 10+ customers for Scorpio X family, expect initial quantities in H2, ramp in 2027

  • Recent public roadmap announcements from AWS and AMD

  Comment: Scorpio-X scale up switch opportunities come from Teton 2/3 PDS and Max racks where Amazon uses PCIe switches to make all-to-all connections on Trainium chips

• UALink (scale up):

  • Solid traction for UALink, incl. product announce, IP availability, compliant methodologies being finalized

  • Initial customer platform ramps in 2027

  • AWS announced in re:Invent that Trainium 4 (ramp in 2027) will support both UALink and NVLink Fusion

  • AMD announced MI 500 will also support UALink in 2027

    • MI 400 series supports UAL over Ethernet

  Comment 1: The 2026–2027 timeframe will be critical in determining whether UALink can gain meaningful traction against ESUN/SUE. ALAB’s fate is quite tied to UALink.

  Comment 2: MI400’s “UALink over Ethernet” is not true UALink - it is essentially Ethernet/SUE.

• NVLink Fusion (scale up):

  • Announced custom connectivity solution (comment: meaning NVLink Fusion) in Q4, feature heterogeneous compute resources

    • Take the native protocol that ASIC speaks and translate into NVLink

  • AWS announced in re:Invent that Trainium 4 (ramp in 2027) will support both UALink and NVLink Fusion

    • See opportunities for add’l hyperscalers

    • Both Amazon and NVIDIA have chosen ALAB as a partner

  • The solution attaches to XPU on 1:1 —> overall revenue in line with UAL switch opportunity

  Comment 1: What ALAB provides is a chip that enables custom ASICs to link to NVswitches through NVLink.

  Comment 2: The key point here is that this business gets ALAB a comparable scale-up revenue per XPU as it supplies UAL switches. Thus, ALAB is largely agnostic to how AWS allocates scale-up architecture between UALink and NVLink Fusion for Trainium 4.

• ESUN (scale up):

  • Scale up protocols will include UAL, Ethernet and ESUN

  • Hyperscalers will leverage the type of solutions that their software stack is designed for

    • If use memory-centric protocol like NVLink/ PCIe, likely continue/ transition UAL later

    • If use Ethernet, likely stay with Ethernet and maybe move to ESUN when available

  • Capability-wise is within reach: we can design an ESUN-based if we choose

  Comment: although ALAB claims from capability standpoint they can switch to ESUN pretty quickly, but I think their success is pretty tied to UALink.

Other future opportunities

• Optical connectivity engines (scale up)

  • Working closely with key clients to define/ develop that for scale-up

  • Ultimately help to enhance both our AI fabric and signal conditioning portfolios

  • Transition to optical connectivity for scale-up could double the merchant scale-up switch TAM

  • Timing should be somewhere in 2028

  Comment: ALAB has not previously done optics. It will be interesting to see how much success they can get in this space - given its strong execution track record, I wouldn't rule out the possibility of its success here. Similarly, another predominantly copper-focused company, CRDO, has also recently launched optical products to counter the long-term shift toward optics replacing copper in scale-up.

• Acquisition

  • aiXscale (Q4): discrete high-density connectors strong interest, being qualified for scale-up

  • Israel Design Center: Q1 closed, acquihire for scale up capability

• Vera Rubin

  • Very minimal opportunity with VR reference design itself

  • Opportunities will come from custom design racks by hyperscalers (what happened with GB racks)

  • We’ve found in every generation of XPU, our content has grown up so far

Today, we take a comprehensive deep dive into the AEC market in data centers. Over the course of this article, you will gain a clear understanding of the following topics:

• Key concepts: retimer chips, reach & latency of AECs…

• Bill-of-material (BOM) analysis of an AEC cable

• AEC vendor qualification process with hyperscalers

• AEC’s comparisons with optical modules

• Shipment volume of 400G/ 800G AECs in 2025 and volume forecast for 2026

• How to estimate future AEC volume based on XPU installment and network architecture

• Pricing mechanism of AEC vendors

• Pricing trend of 400G/ 800G AECs

• The development and production progress of next-generation 1.6T AECs

• Key players in the AEC market (include Credo, Amphenol, Astera Labs, Recodeal, Marvell, Broadcom…)

• How major AEC vendors compare in 3 core competition criteria

• Each hyperscaler’s procurement situation of AECs: procurement volume & pricing, key vendors & their wallet share, relevant clusters & networking architectures…

Section 1: The Basics - Understanding AEC

One important clarification is that AEC is not the only copper cable type with embedded active silicon - ACC (Active Copper Cable) also integrates chips (redrivers) in its cable ends. The key difference is that redrivers only amplify the analog waveform rather than reconstructing it. By contrast, AEC uses integrated SerDes and clock-and-data recovery (CDR) to fully recover and regenerate the data stream, thus providing stronger and more reliable signal quality. Today, the most advanced retimers in production are on 5 nm process nodes and are used in 800G AECs.

Retimers typically account for 45–50% of the total Bill-of-Materials (BOM) of an AEC cable. Note that one cable usually integrates two retimer chips, one at each end, both capable of managing multiple lanes simultaneously due to its parallel SerDes design (for example, an 800G AEC usually consists of eight 100G lanes). Our channel checks indicate a 400G retimer chip typically costs ~$15, while an 800G one is at roughly double the price now.

Apart from the retimers, PCB, together with connectors that physically connect the cable to the switch or compute tray ports account for ~25% of the BOM. While connectors are not hard to produce, reliability is critical to achieving the overall high reliability of AECs. Lastly, the cable itself represents about 20% of the BOM, with the remaining 5% attributable to packaging and other miscellaneous materials.

Reach: The achievable reach of AECs can be up to 7-9 meters at 800G speed. In practice, however, many deployed AECs are much shorter in length - typically 2-3 meters - because their use cases do not require 7-to-9-meter-long connections.

Shorter cables have the advantages of being cheaper, thinner and lighter. At 800G, a 7-meter AEC typically requires a 24-26 AWG, whereas a 3-meter one can use a thinner 28-30 AWG conductor (a higher AWG number corresponds to a thinner wire). The thinness and light weight of cables are important in modern AI data center deployments because they improve heat dissipation and make it easier to route and manage hundreds/ thousands of cables within confined spaces.

Latency: AECs can operate in both InfiniBand and Ethernet environments. The retimer chip adds roughly 1-200 nanoseconds of latency to the cable. With two retimer chips on both ends, the total added latency amounts to about 300 nanoseconds. However, because most AECs today are deployed in Ethernet scale-out environments where ultra-low latency is not the most critical consideration, such latency has generally not been majorly concerning.

Qualification process: To supply AECs to a major customer (typically CSPs), a vendor usually needs to go through a 6-9-month qualification process. During the process, the vendor needs to pass multiple stages, including unit-level tests, system-level tests, and limited-scale pilot deployments to test how its products interop with other components of the client’s network. This lengthy and resource-intensive process creates a competitive moat for leading suppliers, as customers are generally willing to dedicate qualification time and engineering effort to only a small number of potential candidates.

Comparison with optical modules: The main advantage of AECs over optical modules is reliability. Based on industry feedback, the probability of an optical module failing within the first six months of deployment is roughly 1 in 1 thousand, whereas that for AEC is closer to 1 in 100 thousand, a two-orders-of-magnitude difference. A higher failure rate becomes especially costly during AI training runs - when a link breaks, workloads often need to be rolled back to the earlier checkpoint, which can translate into millions of dollars of additional costs. Another key advantage of AEC is lower power consumption - AEC typically consumes 30% less power than optical modules at the same speed.

Section 2: AEC Volume and Market Model

Based on our checks, we estimate a total of 5 million Ethernet AEC cables sold in 2025, with the majority of volume concentrated at 400G/ 800G speeds. Looking ahead to 2026, we expect total AEC demand to roughly double to ~10 million units, with 800G AECs becoming the dominant category.

One key question for investors is how to estimate the number of AEC cables. To do this, the first step is to understand how AECs are actually deployed. There’re two general scenarios for scale out and front-end networks:

• First-layer network: connect XPUs to Top-of-Rack (ToR)/ leaf switches, which represents the most common AEC use case

• Upper-layer network: links between leaf and spine layers, spine and core layers, or both. These connections typically require longer cable lengths as they are usually cross-rack links

In the first layer scenario, the AEC-to-XPU ratio is relatively straightforward to estimate and is basically determined by the XPU’s back-end scale-out (or front-end) bandwidth. For example, in GB200 NVL72, each Blackwell GPU is given 400G of scale-out bandwidth, thus corresponding to 400G AEC per chip at the first-layer. By contrast, GB300 NVL72 supports 800G of scale-out bandwidth per GPU, implying either one 800G AEC or two 400G AECs for the first layer. Beyond this first layer, higher-level network connections are generally implemented using optical modules.

In the upper-layer scenario, the analysis becomes more nuanced. For back-end scale-out networks, traffic is typically all-to-all, meaning that data from the first layer must be fully carried into the upper layers. This implies that the total number of AECs required at each of the upper layers should be the same as that of the first layer.

Front-end networks, however, are usually designed with oversubscription, so not all traffic is forwarded upstream. For example, with a 3:1 oversubscription ratio at the leaf layer, the number of AECs required between the leaf and spine layers would be one-third of those used between the GPUs and the leaf switches. Because oversubscription ratios and topologies vary widely across front-end deployments, AEC estimates for upper-layers should be derived case by case, based on the specific oversubscription assumptions.

Apart from back-end and front-end networks, AECs can also be used in scale-up networks. However, this use case is even more complex, and since it has not yet been meaningfully deployed in practice, I will defer a detailed discussion to a future piece.

Now, let’s try to estimate the total volume opportunities for AECs. I compiled a list of XPUs expected to have the greatest impact on 2026 AEC volumes (including B300, GB300 NVL, R200, VR200 NVL, TPU v7, TPU v8, Trainium 2e, Trainium 3, and R300). For each platform, I estimated first-layer demand by multiplying projected XPU volumes by the corresponding first-layer AEC-to-XPU ratios.

This results in an implied first-layer scale out requirement of roughly 10 million 800G AECs or optical modules, or ~20 million 400G AECs/ optical modules. However, we also need to account for additional XPUs not included in this list, and thus we assume that total volumes to be ~50% higher, bringing the figures to 15 million 800G units or 30 million 400G units. As noted earlier, current market forecasts point to about 10 million total AEC units in 2026, and I will leave it to readers to judge for themselves whether that forecast appears reasonable.

For more detail on the underlying calculations and assumptions behind these figures, please DM me.

Section 3: AEC Pricing

Before getting into the specific pricing levels of 400G/ 800G AECs, I’d like to first address a more fundamental question - How do AEC vendors actually set their prices?

Many assume that a cost-plus pricing method would be reasonable for such a hardware, mass-production-driven industry. However, based on our discussion with AEC companies, pricing in this market is more a value-based approach - leading players such as Credo benchmark their AEC pricing against optical modules at the same speed. The logic is that in short-reach use cases, AEC can deliver comparable and maybe even better results than transceivers, with ~30% lower power consumption and much better reliability (as discussed above). As a result, AECs are priced slightly lower than same-speed optical modules. We think this approach is well-judged and allows AEC vendors to capture more value and margin than they would under a traditional cost-plus framework commonly used by hardware manufacturers.

Let’s look at some concrete examples. In 2025, 400G AECs are typically priced in the $150-200 range, compared with ~$200 for 400G optical modules. Looking ahead to 2026, we expect 400G AEC pricing to trend lower. For example, Credo has already supplied close to 1 million units of 400G AECs to AWS, and as volumes move to such a scale, AWS should be able to negotiate lower prices on incremental orders.

800G AECs have also been sold at elevated prices so far as the product is still in the early ramp-up phase. A 2-meter 800G AEC can cost around $500 even for hyperscale customers such as AWS and xAI, while longer-reach SKUs (5 meters and above) and Y-cable configurations (one 800G fanning out into two 400G ports) are typically priced at $600 or more. In comparison, single mode 800G optical modules are sold at around $5-600 and multi-mode modules are sold at below $400 in 2025. The elevated price points of 800G AECs reflect early-stage supply constraints, combined with strong and urgent demand from multiple hyperscalers for 800G AECs.

Section 4: The Next-Generation 1.6T AECs

AEC vendors have been advancing their designs for the next-generation 1.6T AECs. Current expectations point to an initial rollout around Q2 2026, followed by broader adoption in late 2026. The primary technical bottleneck now lies in 224G-per-lane copper cable manufacturing (compared to the 112G-per-lane cables used for 400G/ 800G AECs), where production depends heavily on specialized German equipment which faces long lead times. Beyond technology hurdles, 1.6T AEC adoption also needs to align with next-gen chip launches. One of the most natural early use cases would be Nvidia’s Vera Rubin chips that come with 1.6T scale-out requirement per GPU.

1.6T AECs are expected to rely on 3nm retimer silicon, which is currently manufacturable at scale only by TSMC and Samsung. Marvell appears to be slightly ahead in bringing 3nm retimers to maturity, while Credo is close behind and still has runway until mid-2026 ahead of the mass-production cycle. With the current generation of retimer chips, 1.6T AECs can reach sub-3-meter transmission distance. Extending connectivity to 7 meters or above, comparable to today’s 800G AECs, would require more advanced next-generation retimer silicon.

Section 5: Key Players in AEC Market

There are broadly two types of AEC vendors. The first category is vertically integrated providers - they design and produce their own retimer chips while also developing and supplying the complete cable assemblies, with Credo as the most representative example. The second category designs the cable solution but sources core retimer chips from third-party designers like Marvell and Broadcom, operating more as a system integrator. Below is a breakdown of the key players in each category.

Type 1: Vertically Integrated Providers

Credo (CRDO): The company is the incumbent in the Ethernet AEC market with dominant shares previously. The company’s technological foundation lies in its SerDes design, which it subsequently extended into AEC retimer chips and DSPs. For 800G AEC retimers, the company offers both 12nm and 5nm options. The more mature 12nm retimer carries higher power consumption (10W vs. 7W for the 5nm version) but is meaningfully cheaper.

As a vertically integrated provider, Credo designs the entire AEC solution in-house and outsources manufacturing based on its proprietary designs. To date, its primary manufacturing partner has been BizLink, but the company is also evaluating the addition of a second production partner - Foxlink - to help handle increasing orders in 2026/ 27.

Astera Labs (ALAB): I wouldn’t characterize Astera as a pure vertically integrated solution provider. It does design and produce retimer chips in-house, similar to Credo, but it often supplies these chips in the form of paddle cards to downstream assemblers or solution vendors. Astera’s current retimer chips are built on 12nm process nodes, whereas competitors such as Credo and Marvell already offer 5nm solutions for 800G. As a newer entrant to the market, Astera has also demonstrated a willingness to price its products below peers like Credo in order to gain market share.

Type 2: System Integrators

Recodeal (688800.CH): The company runs its AEC business through a joint venture with Innolight (300308.CH), in which Recodeal holds a 70% equity stake. Under the arrangement, Recodeal is primarily responsible for product design and manufacturing, while Innolight contributes its established relationships and sales capabilities with U.S. hyperscalers.

Manufacturing and assembly of the JV is done in the U.S./ Mexico and Thailand. The U.S. facilities serve as the main base, where capacity previously allocated to other businesses (like auto) has been repurposed for AEC production; the Thailand operation is a greenfield expansion. The company’s key competitive advantage lies in its cost structure and pricing, which we discuss in more detail in the following section.

Amphenol (APH): The company designs and delivers the complete AEC assembly while sourcing retimer silicon from partners (especially Marvell). It then optimizes the full cable at the system level for signal integrity, thermals, mechanical reliability, and large-scale deployment in AI clusters. Amphenol’s advantage is deep customer relationships and global manufacturing capacity that can support high-volume ramps across regions.

TE Connectivity (TE): Very similar to Amphenol

Eoptolink (300502.CH): The leading optical module vendor is also exploring opportunities to participate in the adjacent AEC market. The company sources retimer chips from both Broadcom and Marvell, but with a heavier weighting to Broadcom due to their close relationships.

Broadex (300548.CH): The company produces and sells AECs through its subsidiary EverPro. It has close relationships with Marvell and is expected to rely heavily on Marvell retimer chips in its AEC shipments. One of Broadex’s key customers is Google, which is seeking to replace some of the DACs used in its 3D Torus architecture with AECs to improve interconnectivity.

Part 6: Competitive Landscape

Which AEC vendors are best positioned to gain share in the highly competitive 2026-2027 cycle? To address this, I compare the key players across three core dimensions that ultimately determine their competitive strength:

1) Retimer Chips

Credo is widely recognized for its top notch analog mixed-signal circuit design capabilities. The company also benefits from in-house chip development, which provides greater design flexibility and tighter integration with other components in its AEC solutions. Based on our checks, Credo’s chips appear advantageous on power efficiency and signal interference resistance, delivering slightly better signal integrity than Marvell’s.

Marvell also has a strong SerDes IP. Its retimer chips are the most widely adopted by AEC system integrators (more than Broadcom’s). The company has a large R&D organization, which shall have helped it progress ahead of Credo in terms of 1.6T AEC retimer development. Additionally, we heard that Marvell’s retimers are typically priced 15-20% below Credo’s when supplied to third-party buyers.

However, for a system integrator, chip performance is inseparable from system-level integration. Beyond the capabilities of the retimer itself, the integrator must also ensure it interfaces and operates well with all other components in the full assembly, so that the chip’s performance can be fully realized in the end system.

Astera Labs’ AEC retimer capabilities are derived from its legacy PCIe retimer technology. The company has strong chip design expertise, and its use of the 12nm process node helps keep production costs relatively low.

2) Mass Production Capability

Among all vendors, Credo has most clearly demonstrated reliable, large-scale AEC production capability, having been the only supplier to deliver millions of high-speed AECs prior to 2025. Its strong execution with customers such as AWS and Microsoft has earned it credibility and helped it secure major 800G AEC orders from customers like xAI.

Another key advantage is Credo’s vertical integration. As a full-solution provider with all designs developed in-house, Credo can diagnose and resolve product issues for customers much more quickly. In contrast, when Amphenol receives client requests, it must coordinate with Marvell on retimer-related issues, which lengthens the issue-resolution cycle.

3) Prices

Due to the value-based framework we revealed previously, AEC pricing across vendors is driven primarily by corporate strategy rather than underlying cost structures. Credo and Amphenol often command premium price points relative to peers according to their market positions. Recodeal, by contrast, is willing to operate at lower gross profit margins (GPM), typically in the 40-50% range, allowing it to gain some price advantages. By comparison, Credo’s Product Sales segment, which encompasses its AEC business, reported a 63% gross margin in 2025. Astera Labs’ AEC pricing also sits toward the lower end of the spectrum.

Part 7: Customers

The primary buyers of AEC cables are hyperscalers. In the final section of the article, I will dive into how each hyperscaler approaches AEC procurement, with specific details on their:

• 400G/ 800G AEC procurement volume

• Main AEC vendors and their rough wallet shares

• XPUs and clusters that use AECs

The hyperscalers covered in this section include Microsoft, Amazon, Google, Meta, xAI, and Oracle.

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