Extra Intro Note:

Thank you.

Never expected to make it this far.

100% of content will always be free. The pledge thing is for a theoretical future donation box. A backup in case my dumbass gets fired and blacklisted from industry.

But honestly, this…. hobby…. is now net positive for my career lol. Life it seems is stranger than fiction and some things going on behind the scenes. Don’t have to worry about being fired and unemployed anymore.

Hello and welcome to a brief note on two completely unrelated topics. Recently read an excellent article by on coherent lite transceivers. (not to be confused with the corporation named Coherent or the other corporation with ticker LITE…)

FundaAI

Deep|Coherent Lite Reshapes AI Optical Interconnects

Key Takeaways…

Read more

12 days ago · 31 likes · 3 comments

Go sub to them. I am a paid sub on my real substack account.

One table bothered me….

EML having less area than a low-power CW laser is obviously wrong. Then there is the area issue. Photonic chips, particularly lasers and InP, tend to be narrow and long. So using area intensity is problematic. Need to use a wafer map calculator.

After spending half an hour running some quick sanity checks, I realized this table is completely wrong lol.

But Funda’s conclusions are mostly correct. Marvell biggest winner. Other investment conclusions also correct but InP intensity not as high as they think.

One core theme of the Funda piece is InP PIC for coherent lite. I can tell you that Tx will not be InP monolithic. Rx, there is nuance. I did some basic calculations on how much InP would be eaten if both Tx and Rx of coherent lite is monolithic InP and quickly realized this is crazy town. InP situation is already an unmitigated disaster. Adding this extra demand on top is like pouring all the stranded crude oil in the strait of Hormuz onto an existing InP dumpster fire.

Funda friends were kind enough to share the PDF of the Google paper (OFC 2026 tutorial) related to this topic.

https://x.com/phasentrpolator also sent me a great paper. Spent a couple hours flipping through textbooks and got enough material to work with.

Contents:

1. Coherent Component Crash Course

2. Google Paper Quick Overview

3. Summary of FundaAI’s Arguments

4. Wrong Parts

5. InP Yield and Area Crash Course

6. Irrational Analysis InP Intensity Model

7. Theoretical Optimal Coherent Lite Design

8. Winners and Losers

9. [Bonus] AMD CPU Opportunity

10. Trading Account Snapshot: 06/13/2026

[1] Coherent Component Crash Course

I don’t want to bore you too much with how Coherent transceivers work. My primary objective is to teach you what the unique (compared to traditional IMDD) components are, why they exist, and how they affect system design.

If you understand the structures, you can easily understand the delta between coherent and coherent lite.

Fundamentally, coherent optics is the same as how wireless communication systems work. Data is encoded on two axis (I and Q), transmitted, and decoded later.

Another way of looking at this is as follows.

How to transmit complex numbers in the real world?

(use a sinusoid + 90 deg phase shifter to mix each channel)

The benefit of this strategy is a lot more bits per symbol. Wireless goes up to 1024QAM these days. Optics seems to stick with 16QAM.

In a previous life I worked on 1024QAM 5G/6G bullshit. Stupid feature. Tx EVM of commercial base stations cannot support unless ultra ideal conditions and even then not at max coderate.

Anyway, we know the benefit, so what is the drawback?

PHASE NOISE MANAGMENT

All components intrinsically have phase noise. Some more than others. Here is what your constellation looks like when phase noise is allowed to run amok.

You get a useless doughnut.

Phase noise problems are very difficult to debug and design around. Often the solution is “just use more expensive components bro”. Alternatively, people use complex (very area and power expensive) DSP (math) to characterize the phase noise of the system and back-out that transfer function in Rx EQ.

Always remember that engineering is all about tradeoffs. Understand these tradeoffs and you understand why people make design choices.

Back to coherent optics, the LO in this case is a laser. The noise performance and polarization of the LO laser (ok every laser in a coherent system) is critical.

Laser linewidth is a measure of phase noise.

Phase noise is super bad in coherent systems, so the linewidth requirements are very strict. Easily < 0.2 MHz.

Managing phase noise, is painful. Trust me on this.

Leveraging symmetry is critical to removing LO noise. If both arms and photodetectors are precisely matched, large portions of the LO laser will be canceled out.

On the flipside if you screw this up everything becomes garbage and is unfixable.

RIN kills you.

Linewidth kills you much harder.

[2] Google Paper Quick Overview

Bottom (C) is a normal coherent transceiver architecture).

Top (A) is coherent lite.

Middle (B) is ugly, unnecessarily complex, and just worse than (A).

The fundamental delta between coherent and (polarization-folding) coherent lite is… polarization so let’s take a quick detour.

Polarization is the angle of light. Sunglasses work by filtering out some angles.

In optics, the nomenclature for polarization is TE and TM.

Broadly speaking, photonic structures (on Silicon, Silicon-Nitride, Indium-Phosphide, …) have one of three states:

1. Only accept TE mode.

2. Only accept TM mode.

3. Does not care about polarization.

For example here is a structure that rotates light from TM to TE.

And here is a structure that separates TE and TM modes.

Broadly speaking, dealing with polarization on SiPho is much more annoying than InP…

… at the cost of area. Remember, tradeoffs.

Now let me annotate the Google coherent lite block diagram to help you understand why it represents beautiful engineering (good tradeoffs).

Notice how nothing in the Tx block diagram involves polarization. This is a good thing!

Massive cost-down enabled by SiPho PIC.

The key to understanding coherent lite is polarization-folding.

Why go to the trouble?

The answer is surprisingly simple.

The transmitter output it going to have random polarization. If you get unlucky, the receiver will get very little light because most of the light is on the wrong polarization/mode.

The entire receiver in coherent lite is designed around a specific polarization (prob TE). We cannot afford to waste light/energy trapped in TM mode.

Very clever trick. Dramatically reduces complexity and cost on Rx.

The DSP needs to do some extra math though. Intuitively, the transfer function of the polarization folding unit is 1 + Z^-1. Dug up the partial response signaling paper out of curiosity…

Yea this is straightforward. Use all energy, force it to be on TE mode, and have the DSP back out a simple transfer function before running anything else.

[3] Summary of FundaAI’s Arguments

1. Coherent lite is going to be huge because of Google.

2. Driven by OCS insertion loss budget.

This is correct although 3 dB loss on MEMS OCS sounds high. Wonder what size of OCS switch induces such loss.

[4] Wrong Parts

Now for the wrong parts.

This is completely wrong. Transmit is not more complex. Line rate for each MZI drops to 168Gbps. SiPho already works at 224Gbps line rate.

168 is in fact a smaller number than 224.

Nothing in the transmit side is polarization sensitive. There is no need to use InP. SiPho will do just fine.

(Tower Semi sipho, not that GloFo dogshit)

A MZI modulator can easily hit 5 mm long. Using InP for coherent lite Tx PIC would obliterate the industry. Also would obliterate cost.

I will come back to the estimates. Entire FundaAI table is wrong as a reminder. I’m not kidding or trying to be mean. All the numbers are wrong.

[5] InP Yield and Area Crash Course

Indium-Phosphide is a satanic nightmare. As a ballpark, yield of 50% is considered normal for discrete devices (CW laser, EML).

Unlike silicon/logic, there are no tuning parameters to harvest parametric issues.

Some of your InP devices will be at the wrong wavelength. Too far away from target to thermally tune via TEC. You fucked.

Some InP devices won’t hit target power at target temperature (typically 40C or 50C). Nothing to be done.

Some InP devices will be flaky, exhibiting erratic behavior at target setpoint. This is called mode hopping. Can’t do anything. YAY INDIUM PHOSPHIDE IS AWESOME.

Also InP is a very brittle material. Lots of dice die as you try to package and wirebond.

[6] Irrational Analysis InP Intensity Model

I have build a model using numbers pulled from my anus. Maybe I know things. Maybe I don’t. Wink wink.

[7] Theoretical Optimal Coherent Lite Design

It is unclear to me what the actual architecture will be but here are my best guesses. The design space is pretty open.

1. Tx

   1. DFB (no ITLA)

   2. Tower Sipho with MZI modulators.

   3. Each modulator signaled at 168Gbps.

   4. Marvell or Semtech Drivers

2. Rx

   1. Monolithic InP PIC (Coherent the corporation or Nokia)

   2. TIA from Marvell or Semtech.

3. DSP

   1. This is Marvell.

   2. 8x 336G PAM6 SerDes receive from host

   3. 16x 168G PAM4 SerDes to PIC

[8] Winners and Losers

Marvell is the biggest winner by far. They gona make so much money on the DSP and have great driver/TIA bundling oppertunities.

Tower wins because more sipho and GloFo is actually incompetent.

Semtech win but maybe not as much as I hope. Marvell might take most of the sockets inside the transceiver.

Macom lose because photodiodes integrate into InP PIC.

Coherent (the corporation) and Nokia win with 6in InP process for monolithic InP PIC. Other InP players won’t want to burn their 4in capacity on this.

[9] [Bonus] AMD CPU Opportunity

Suppose AMD gets more wafers from TSMC. Assume this but don’t think about it, unless you were on the recent Raymond James bus tour.

Thos incremental N3P wafers would all go to datacenter CPU, the hottest and by far highest gross margin product line AMD has.

Been chatting with some contacts and I don’t think any of them understand the money tsunami Dr. Lisa Su is capable of unleashing IF AND ONLY IF SHE GOT MORE N3P WAFERS.

AMD Turin uses N3P for the CPU core chiplets and N6 for the I/O die.

By far the best implementation of chiplets. Their numbers are dirty. Let me show you.

[10] Trading Account Snapshot: 06/13/2026

First, congratulations to Matt Murphy and the non-trivial number of Marvell employees who are subscribed.

Up 60% in one week lol.

Don’t worry about me I was not short.

Gave up trying to short back at $172.

Marvell is by far the most asked about stock from institutional investors. There are at least 10 hedge funds and 3 family offices who constantly ask me about this ticker.

I don’t know what is happening.

But I will write a public note on some best guesses. Please friends lets talk about something more interesting. AMD is interesting.

No, I am not going to buy into Marvell. In truth, AMD CPU story is more interesting and I am debating on sizing up the position. You will see my trading book and long-only book at end of this post. Generally happy with the state of everything but need more Samsung, considering more AMD, and want to buy back into Ciena but too levered and AMD probably takes priority.

Contents:

1. Politics and Conspiracy Theories

2. Dense SRAM

3. DDR4 CXL Re-Use

4. Holdings Update

[1] Politics and Conspiracy Theories

Jensen $2B into Marvell has vastly out-performed his own stock. Why buy-back shares when you can make meme investments in competitors and suppliers?

The motivation of Mr. Leather Jacket is unclear. I have some guesses but zero conviction behind said guesses so take with large grain of salt.

• Force Amazon to use NVLink Fusion instead of Celestial?

• Block AMD from custom high-performance switchs?

• Weaken Broadcom?

• Get access to Celestial IP as a backup plan if ring modulators don’t scale?

• Get access to Marvell dense SRAM IP?

There was quite a bit of friction between Nvidia and Marvell over optical DSP pricing and performance. Nvidia has their own internal DSP which seems pretty good (recent OFC demo) but may or may not be designed into 1.6T transceivers. So much drama around this I gave up. Waste of thinking time.

[2] Dense SRAM

Marvell showed excellent results of their custom dense SRAM IP at Hot Chips last year. In truth, I don’t understand how it works but the data they showed is rock solid and excellent. Only caveat is their comparisons are against (my guess) Synopsys stock IP. Nvidia, AMD, and have better internal SRAM IP but maybe Marvell’s is still a lot better.

They can run at 500 mV (450 if you push it and ignore cold corner) which is kinda incredible. Usually the floor is around 630 mV… maybe 600 mV.

Licensable = Synopsys

Still, gap is so wide this IP is probably better than most if not all internal SRAM IP from Nvidia, AMD, Broadcom, ect.

This data is super legit. Not cheesed. Just want to point out that in this plot the lowest voltage corner is at 630 mV for N3 while the previous data was for N2. If you ignore < 10C as an operating condition (reasonable for datacenter) then they can drop the voltage way more.

[3] DDR4 CXL Re-Use

At the time of the Hot Chips presentation last year, I viewed CXL as a dead technology. With DRAM going to the moon, well now view has to change.

When old CPU servers are de-commissioned, the DDR4 is not useful anymore. Say you consolidate 3 old DDR4 CPU servers into 1 DDR5 CPU server. That DDR4 usually gets fire sold on eBay or scrapped.

With Marvell Structera (CXL card), Hyperscalers can re-use all that DDR4 in a memory pool. Sure, the latency is dogshit but its way better than NAND storage and DRAM prices have gone exponential with a crippling shortage.

Amusingly this Structera product went from worthless garbage to extremely valuable and it seems nobody has noticed.

This one is for DDR5 but they have a DDR4 version as well.

Not kidding, Marvell’s highest gross margin product is probably the DDR4 Structera card and this most profitable chip is gona go from zero to a large revenue number.

In a world where DRAM prices have gone up like crazy and there is a crippling historical shortage, the residual value of old fully-depreciated DDR4 DRAM sticks from old de-commissioned CPU servers is extremely high.

Marvell can probably charge like 85% margins on this Structera chips and get away with it. The value of re-using old DDR4 sticks is so high nobody will complain.

Astera Labs is the other CXL play but the Marvell product is just better. Way better interface IP than the Synopsys stuff Astera licenses. And remember, dense SRAM! You want SRAM as a cache to hide the latency of the CXL controller.

[4] Holdings Update

I am in the process of finishing up a (rare) re-balance of the long-only accounts. Would say 90% of the way there. Want to make Samsung a > 5% position but perhaps it will have to wait for cashflow via dayjob. Maybe cut GEV in half again and send proceeds to IBKR for buying moar Samsung. Trading account generally happy but want to size up AMD… a lot. Still thinking this thru. Also, I have no plan on how to pay the estimated $56K in tax pre-payment due by July 15th. Problem for future me.

Also if Ciena shits itself this week from earnings I will buy back in. If they moon I will also probably FOMO in anyway. Very unhappy with how I played Ciena this year.

Welcome to an updated view (partial capitulation) on memory. Specifically DRAM. Nand/flash is outside the scope of this post. Go away Sandisk bulls.

I have been negative on DRAM (Micron/Samsung/SK) as an investment due to persistent fears of cyclicality.

There are two camps:

1. Team price/book

2. Team price/earnings

Each side thinks the other is completely retarded.

Still consider myself in team price/book but… willing to make an exception and consort with the other side temporarily.

Funny story….

Two years ago at GTC 2024, I was at one of the after-parties waiting to meet Doug for the first time in real life. At the party, Dylan and a few random hedge fund people were chatting. One of the hedgies was talking about how his PM/boss said “if you see a bubble forming, run towards it”.

*This quote is from George Soros. Random hedgie minion def does not work for Soros so he mis-attributed the quote.

Spicy Takes:

1. I believe HBM is a mistake and will be phased out (90% drop in volume from peak) within the next 7-10 years.

2. DRAM stocks prob have another double or triple left in them.

3. At some point in the next 3-10 years, DRAM stocks will drawdown at least 70% from peak.

Contents:

1. Engineering

   1. HBM is a mistake.

   2. [short term] Hybrid-bonded HBM is necessary.

   3. [partial solution] CXL

   4. The optimal (future) approach.

2. Entertaining History

3. Agentic Reality: Featuring Nick/Coatue

4. Pitch: Samsung

[1] Engineering

Let’s start with engineering topics. Some level of background is needed.

Memory is in two categories:

1. DRAM

2. NAND aka Flash aka NAND Flash

Within DRAM, there is DDR, LPDDR, GDDR, and HBM. I view all of them as equivalent and you will see why shortly.

DRAM, NAND, and logic all have separate process technologies. The factory capacity is not fungible.

All DRAM works the same in principal. A transistor controls the charge of a capacitor. Reading the bit drains the capacitor. The capacitor also naturally loses charge over time so it constantly needs to be refreshed. This is why DRAM is referred to as volatile memory, it needs power to store data.

DRAM has only four core attributes:

1. Latency

2. Bandwidth

3. Capacity

4. Power Consumption

Changing the structure of the grid of capacitors and transistors gives you DDR vs LPDDR vs GDDR but it really is all the same at a high level.

HBM is different because there is vertical stacking.

Some of the DRAM die area is occupied by TSVs (through silicon vias), vertical wires.

There are also micro-bumps to connect the dies together.

HBM (high-bandwidth memory) gives you high-bandwidth, but at a high cost. This cost (economic, thermal, power) is going up at an untenable pace.

Don’t believe me? Take a look at the Rubin HBM4 fiasco.

JEDEC is the standards body that governs DRAM. Generally, when a new spec comes out (DDR5, LPDDR5X, HBM4, whatever) there is an initial speed agreed to in spec and over time industry adopts higher speeds over time.

With HBM4, JEDEC spec said 8 Gbps/pin and immediately Nvidia Rubin (first product to ramp) demanded 11 Gbps/pin. All three major HBM vendors (SK Hynix, Samsung, Micron) proceeded to fail to meet this request at various severities. Endless drama from the supply-chain leaker degenerates.

The root cause of this fiasco is simple. Bump capacitance. Will get to that in a later section.

HBM4 rollout is an industry-wide fiasco.

JEDEC are idiots for releasing a spec that is immediately obsolete.

All the consumers of HBM4 look like fools for making last-minute demands that cause chaos and delay their own roadmaps.

All the HBM vendors look stupid for claiming they can meet 11 Gbps or 10 Gbps then failing Nvidia qualification process because none of them know how to use high-speed probe stations.

[1.a] HBM is a mistake.

Memory bandwidth is an I/O density problem which has been solved in the wrong way by the wrong people.

You see, 11 Gbps pin speed is still… shit compared to everything else on the market outside of DRAM-land. 32G short-reach SerDes (UCIe AP, NVLink D2D, Marvell D2D, Broadcom MAX) are ubiquitous. Hell the 64G class versions are either already in prod or close.

DRAM crowd was given a PHY problem and botched it. Now, other companies are making custom solutions to bypass the fail. See this example from Marvell.

Diagram is not to scale and just illustrative but the point is clear. If you don’t use a retarded PHY, you can save a lot of ASIC shoreline and shove more of them in. Orange box gets smaller.

In this case, beachfront width does not improve because the TSVs of the HBM still limit even though the custom Marvell PHY is way better.

There are gains to be had from custom HBM base die. Marvell claims 25% more bandwidth. Great… but people want way more. AI is insanely memory bandwidth bound.

Key Points:

1. HBM PHY is dogshit.

2. Custom HBM base die partially mitigates this issue.

3. The TSVs are the real limit, locking up precious shoreline.

There are a variety of startups trying to solve this memory bandwidth issue. Some go for SRAM-heavy designs. Others use exotic processes. There is one startup that is my favorite and that is Positron. They solved this problem the “correct” way.

Unfortunately under NDA so can only give vague info that Thomas already shared publicly.

• Positron does not use any HBM.

• Only use commodity LPDDR5X.

• Highest memory bandwidth of any AI ASIC.

• Some clever architectural tricks to actually use all that bandwidth effectively.

Also know everything about Etched but under NDA. Architecture is very cool but they still suffer the same HBM limits as everyone else. Hopefully in the next few months I can negotiate proper coverage.

Positron gave me all their slides. Etched showed me the material but still wont send the PDF. MatX wont give me anything so IDK maybe I need to threaten them. Those Pope podcasts are useless and have zero real information.

Positron is the only startup that has properly addressed the memory bottleneck in my opinion. There is a better way that involves optics but in the short term, Positron’s approach is optimal.

[1.b] [short term] Hybrid-bonded HBM is necessary.

The HBM4 fiasco was driven by two primary factors, base die and pump capacitance.

Samsung used their internal SRF4X logic node (perf ~TSMC N6/N7P) and had the easiest time. Enough margin from the transistor performance to fix issues quickly.

SK Hynix chose TSMC N12 and… had like 6 re-spins.

Micron went full retard and tried to stay on internal DRAM process node for base die.

But even with a good base die, there is still the parasitic bump capacitance issue.

Let’s look at some squiggly lines!

This is a TDR trace (time domain reflectometer):

You can use a machine to map out the impedance of a system. Stare at enough of these squiggly lines and it becomes second nature to spot what part of the system made what part of the plot.

Probe a HBM stack (without the base die) and you will get a TDR trace with one spike per layer. The spikes correspond to parasitic bump capacitance.

Only way to (properly) fix this is to move to hybrid bonding.

Everyone keeps viewing hybrid-bonded HBM from a thermal or stack height perspective… which is valid.

My point is speed/performance is the real gate and what will finally push DRAM vendors to suck it up and use hybrid bonding.

Think of capacitors as speed bumps. You can make the base die as amazing as possible but those parasitic capacitors in the stack will kill your signal. Either blow up PHY power or accept lower speed.

Speaking of which… this SK Hynix innovation is more evidence HBM is a mistake.

Why yes, the PHY power is gona blow up as speeds go up. Your solution is to have an overhang and place a thermal conductor pillar.

This is like trying to eat while wrapping your arm behind your head. Technically possible but stupid.

HBM is a mistake. The solution is to disaggregate memory with a real PHY that drives co-packaged optics.

[1.c] [partial solution] CXL

CXL is a protocol built on top of PCIe that allows for memory expansion and pooling. Initially designed for CPUs, it was abandoned. Now it’s coming back.

Great for Marvell and Astera Labs.

But still does not solve the problem properly. Remember, we have a PHY problem and CXL is just a protocol built on top of a sub-optimal PCIe PHY.

[1.d] The optimal (future) approach.

At ISSCC 2026, Nvidia showed a glimpse of the future. The correct approach to I/O beachfront problem, and by extension the memory bandwidth problem.

Clock-forwarded SerDes directly driving optics.

On the ASIC side, you have essentially no latency added to the system as there is no re-timer or need for a heavy (latency inducing) FEC. Shoreline density of clock-forwarded XSR SerDes is very high. Optics enable reach from 1 to 30 meter easily, once you go through the pain and suffering of getting the data on the optical fiber.

Clock forwarding allows for the entire Rx EQ to be gutted. No CDR, FFE, DFE, MLSE, or compound CTLE. Just a simple TIA.

Sub 3 pj/bit, up to 10 meter reach easily. More likely 30 meter should work assuming chromatic dispersion does not mess with the delay compensation circuitry.

Shoreline density is not great and you need to look at the die shot to see why.

Each lane is in an 81 micron square. The Tx/Rx PLLs are the same size as an entire lane AFE. This does not make sense from an electronics perspective. My guess is photonic issues, particularly thermal crosstalk, forced the EIC to blow up in area. You can see the digital backend and JTAG separating Tx and Rx AFE. This was likely intentional to isolate ring modulator self-heating from Tx rings polluting Rx rings. Point is, the end state of this technology at commercialization is (well… should) going to be way better than 0.4 Tbps/mm unidirectional.

Because the system is optical, you can just route with an OCS that also has effectively no latency when compared to a traditional electrical switch.

On the device side, all you need is a chip that converts optical back to electrical (minimal latency) followed by some LPDDR PHYs. The latency will be dominated by the LPDDR PHY and controller. Perhaps clever optimizations will be enough. Perhaps a stack of HBM somewhere in the system used as a cache will be needed.

But this is the future in my opinion. Optically attached, disaggregated LPPDR memory pools. Nvidia is 2-3 years away from implementing this at scale. Broadcom and Marvell 3-5 years.

The benefits are enormous. Way higher bandwidth/mm shoreline density. Way more capacity. Minor latency penalty if done right. And most importantly, the ability to re-use and re-allocate DRAM across chips instead of packaging them forever with the ASIC while also enabling the ASIC to draw more power due to higher thermal headroom.

It get’s even better. You probably have heard of the HBM trade ratio. How many GB of regular DRAM capacity is consumed to produce 1 GB of HBM.

It is like 3:1 or something. The actual number does not matter. Its a big number. Massive supply destruction has HBM mix goes up.

If that reverses, you would think the DRAM vendors would get screwed but I disagree.

Right now, they are making 80% ish gross margins. At that profitability, all the customers know they are getting screwed and are thus unhappy and strongly incentivized to find a way out.

Imagine a world where HBM is replaced by LPDDR, DRAM supply is 3x, gross margins go down from 80% to 60%.

Everyone wins in this scenario.

DRAM makers end up with 2.25X profits (do the math retards) with 3x revenue at modest margin cut while also not pissing off all the customers.

DRAM customers get 3x supply at much more palatable prices to satisfy insatiable agentic AI demand.

DRAM customers also don’t have to worry about advanced packaging yield as much and can scale their logic chips more instead of wasting space on HBM stacks.

[2] Entertaining History

To understand the history of DRAM companies, you must read the transcripts of past earnings calls. This is typically a boring process so to keep people interested, I will roast Sanjay Mehrotra (Micron CEO) for entertainment purposes. There is a particular feature of Micron earnings decks that makes this goal easier to achieve.

We are going to look at every earnings call transcript from June 2017 (first call with Sanjay as CEO) to June 2025, the last earnings call where a negative dip happened before the crazy rally started.

You really should read this section in it’s entirety. It’s important.

June 2017: $30/share

Sanjay did time his join date of March 2017 well. It was at the bottom of the cycle. 2017 cycle was particularly nice for the DRAM players. I remember as I was in college trying to buy DRAM for a gaming PC build. Fucking DDR tripled in price or some shit.

Sept 2017: $39/share

Ah yes, strategic value, not a commodity. Yes Sanjay pump your RSU.

Dec 2017: $43/share

One of the biggest red flags you can see is mentioning cost competitiveness in one sentence then literally mentioning high-value in the next sentence. It is a sign of someone who knows he is selling a commodity but wants to pretend otherwise.

Mar 2018: $57/share

Well buddy the cycle is about to turn so I hope you got some of those high-value solutions to insulate you.

June 2018: $60/share (TOP OF CYCLE)

Ah yes starting buybacks at the top. Great start.

This time is different guys. Stability in the market!

You can see the Nomura analyst shitting on Micron management. Thanks for keeping important negative guidance info at the end of the presentation you little shits.

Guys it’s just a 1-quarter blip. Next quarter prices will be healthy again. This is def not peak cycle and we certainty are not gona crash.

Are your gross margins deteriorating because of price cuts (very bad) or mix shift (ok excuse).

Hint: it was because of price cuts. OVERSUPPLY BAYBEEEE.

Analyst: Is this cycle (2017-2018) different this time?

Sanjay: Yes.

(it was not different that time)

Sept 2018: $45/share

Sounds like youssa in a down-cycle.

Dec 2018: $32/share (CYCLE BOTTOM)

Oh look this time was not different! Youssa eating shit in downcycle and resorting to decisive (desperate) actions.

Datacenter NAND/SSD is going to be great for us.

Also we are going to eat shit in this exact segment for the next year.

O V E R S U P P L Y

June 2019: $42/share

Ah yes you finally said the dirty word.

OVERSUPPLY

We made it past the usual euphemism of “inventory adjustment/digestion”.

The last sentence is a public call for Sanjay’s degen Korean friends to have mercy.

Sept 2019: $46/share

Amusingly this was probably true… and only a few months later COVID lockdowns hit right after inventory over-stocking due to tariff fears.

Dec 2019: $56/share (local* top in upcycle)

*due to pandemic. Under other circumstances upcycle would have continued prob another 12-18 months cleanly.

Stocks are forward looking. Smart people (not me lol) predicted when the bottom would be in and bought 6-8 months before Sanjay said the above quote.

Mar 2020: $44/share

The next few quarters will be skipped because COVID bullshit distorts everything. All you need to know is the following events roughly played out:

1. Collapse in demand at the beginning (fear)

2. Then an explosion of demand because work-from-home, bored people, stimulus checks. (the “COVID pull-forward”)

Let’s skip ahead 9 months to happy Sanjay riding the COVID consumer electronics pull-forward wave.

Jan 2021: $78/share

Mar 2021: $92/share (CYCLE 1st TOP)

This is true. COVID pull-forward did hit all sectors same time.

Jun 2021: $81/share

C. J. Muse is (correctly) pointing out that some bad omens are out there and Sanjay literally takes the opposite stance. Nonono demand for memory gona go up even more! Nothing unsettling to see here.

Joe Moore also smells blood. He is re-asking C. J. Muse question in a more subtle way to try and pin down Sanjay.

Sep 2021: $71/share (miD-cycle local bottom)

Again, the specter of over-supply (driven by COVID PC demand pull-forward) comes up.

Dec 2021: $94/share (CYCLE TOP)

I like to imagine Sanjay smoking a Cuban cigar during this call. Next two years are not gona be fun. Well not fun for him. Hilarious to me.

(PC would continue to implode lol)

You can C.J. Muse trying to warn everyone and Sanjay spouting bullshit.

Mar 2022: $78/share

Everything is fine guys. Nothing to see here.

As an aside, Zinsner got out at the right time. Good for him.

Jun 2022: $56/share

Not quite the bottom but getting there.

Oh so sell-side was correct three months ago and Sanjay was still off in la-la land?

You clowns told everyone PC was fine 90 days ago. Oh no its just chromebooks blah blah enterprise PC great. Idiots.

Slashing wafer starts. Let the panic begin!

Sept 2022: $50/share

Oh would you look at that, Krish Sankar of Sell-Side was correct that datacenter would be next shoe to drop. I guess Sumit Sadana is either incompetent or knowingly spouted bullshit 90 days ago.

Translation: we about to party like it’s 2001. Yea, that bad.

COVID pull-forward is finally hitting hard the other direction.

UNDERUTILIZATION LEZ GOOOOO

Mid-single digit utilization cut. Remember this number.

(Hint: it’s going up)

Vivek calling bullshit and Sanjay has to back-off rosy language on PC.

This is the key passage. Samsung is not cutting expansion plans. Everyone knows this. Micron is trying to avoid talking about this but the assumptions of their own guidance have Samsung expansion baked in.

Dec 2022: $51/share (CYCLE BOTTOM)

Ok… 90 days ago you said on the last earnings call wafer starts cut mid single digits. Now that is up to 20% LOL.

Samsung is not cutting at all. This was at the low-point for Samsung Logic Foundry so the Device Solutions group was extra degen trying to gain share in DRAM to make up for logic failures.

Well at least he gave a straight answer. Kudos for that.

Mar 2023: $61/share

For those of you wondering why the DRAM vendors have not taken Hyperscaler offers for assisted CapEx, this is why. They nearly killed each other ~3 years go.

Sanjay is well aware that Samsung is the reason supply discipline has been fucked for last 2-3 years.

Jun 2023: $67/share

Well we started at mid single digit and now at 30% wafer start cut LOL.

Remember though stocks are forward looking. Micron already bottomed six months ago.

Sept 2023: $70/share

Still guiding for negative gross margins but remember stonks are forward looking.

Dec 2023: $86/share

Trending in right direction.

Mar 2024: $114/share

Back to good utilization and HBM trade ratio starting to destroy supply.

The trade ratio stuff was correct but there is one more dip before Valhalla.

Jun 2024: $133/share (local top, driven by HBM hopium)

Micron made a lot of noise about their HBM3e but it turned out to disappoint finance crowd.

The correction back to ~100/share was due to missed HBM3e expectations. Then we had liberation day that liberated my portfolio from gains. Then DRAM went vertical.

Sept 2024: $107/share

In truth I am tired so gona finished off this section half assed. There was some noise on Micron HBM3e qualification then even more noise on HBM4 qualification but in the end none of it mattered. Moon bitches.

[3] Agentic Reality: Featuring Nick/Coatue

What finally got me to change my negative view on DRAM is a very nice video by Nick/Coatue.

It’s a two minute video go watch it.

The thing is, someone told me a very similar thesis back at MS TMT when Micron was at $400/share.

• Agentic AI adds huge structural demand.

• Memory moon.

• DRAM companies re-rate from price/book to price/earnings valuation.

At the time, I thought this person was a raving lunatic. Obviously very wrong…. but the question is…

Too late or more juice to squeeze?

If you go by the historical DRAM cycle length, we should be near peak cycle but because of AI agent demand (not a pull-forward of human demand) it is reasonable to assume the top is at least 18 months away from the time of writing (May 2026).

If you believe in agentic AI being a real, permanent demand driver, does mid-single digit P/E make sense for DRAM vendors? These guys are making so much money the forward book value is not terrible lol.

Sure there will be an overbuild and a cycle just like always. But this will be the longest cycle ever, with the most entertaining drawdown. But that is a problem for 18-months-from-now me to figure out.

A few people pinged me on May 11th that Coatue are idiots who top tick sectors like SaaS.

Congrats guys you were right. They did top tick memory but not in the way you were implying.

[4] Pitch: Samsung

So which of the three to choose? My views are closely aligned with Mustached Dr. Lisa Su, AKA TBU.

Samsung is the only DRAM maker with an in-house logic foundry and (more importantly) experience with interface IP and logic development.

I am very familiar with SF4X. At PPA level, it is competitive with TSMC N7/N6. Area is the biggest problem with that node. PFETs are also super leaky for some reason.

For first generation HBM4, SK Hynix chose TSMC N12 (wrong… why did you not pick N7…?) and Micron idiotically went internal DRAM process base die.

Going forward, SK Hynix and Micron will both have margins suffer from TSMC N3 base die and more importantly, neither has experience with logic design or high-speed signal integrity.

Samsung Device Solutions (logic foundry + DRAM + logic design) has lots of experience. Samsung in-house NVMe controllers are quite good.

What’s even better is Samsung Device Solutions has an internal silicon photonics process node and SiPho CPO design group. They had some decent papers at OFC recently. Not joking, I think Samsung Foundry SIPho is ahead of GloFo and S.LSI CPO group is ahead of AMD CPO group. This is partially a compliment towards Samsung DS, partially and insult towards GloFo and AMD.

Co-design opportunities are abundant.

Rember the TDR traces I showed you earlier?

The frequency domain representation of the same thing is called s-parameters. Covered this in more detail previously many times go read backlog.

At a previous Hot Chips conference, Furiosia AI showed the s-param plots of their package design. (thank you Furiosia people, nobody else publishes these things publicly… very annoying)

These are s-param plots for the package. (channel between ASIC and HBM base die)

There is another channel between the base die and the DRAM dies above. Those s-parameter plots are secret. I know roughly what they look like from experience but the exact magnitude of the impedance mis-match due to each layers bump capacitance and overall uniformity of the parasitic across each layer of a HBM stack is unknown to the public.

Samsung Electronics is in a unique position to aggressively co-design HBM PHY and TSV PHY to optimize DRAM design, HBM stack/process design, and interface IP design across electrical and optical.

If you know the channel ahead of time and can accurately model process variation of the channel, the SerDes can be aggressively optimized for that particular channel. THIS IS WHY NVIDIA NVLINK IS AHEAD OF EVERYONE. THEY DONT NEED TO INTEROPT. THEY CONTROL PACKAGE, PCB, SERDES, CABLES, EVERYTHING IN ENTIRE BIANCA/KYBER/WHATEVER PLATFORMS. NVLINK IS ETHERNET WITHOUT THE GENERALIZATION OR INTEROPRABILITY.

Now for stonks. I currently have no DRAM related position. Considering my options. Generally want to size it as $100K entry with option to double down and put another $100K. Only have direct access to Korean equities in un-levered long-only IBKR account so my personal list of options are:

• Re-balance holdings, send $100K to IBKR account, buy Samsung equity.

• Put $100K into KORU degen 3x levered Korea ETF in trading account.

• $50K of micron calls (6+ month expiration) but the options chain looks like ass so unlikely.

Still debating this. Also to the uh…. 20+ finance people who have pinged me about memory over the last few months, please let me know what you think about Samsung » SK Hynix and Micron thesis. It’s more efficient to ping all of you simultaneously lol.

Seems like no-brainer to me. Cheaper on book value. Multiple structural engineering advantages.

Ok kicking myself for forgetting this one in the recent SiC/GaN post.

One very useful component is the supercapacitor, a giant capacitor. Mainly for energy storage as a rapid response alternative to batteries. These things are not for traditional capacitor uses (filtering/de-cap). Separate niche. I know the ESR is high, go away.

Exponentially growing niche lol.

I own some shares from like a year ago in one of the long only accounts and sort of forgotten about them. Position was down like 25% at one point but is now up 57% even after I bought some more this week.

Honestly don’t own nearly enough. Want to double position but no free cash.

Anyway I am super busy so this post has a 1 hour time limit. Last year I did a detailed analysis of 10+ supercapacitor companies (for myself, did not publish it) and concluded that $7220.T vaporizes everyone else. So will only include second place here in the interest of time.

This is an uber monopoly of a rapidly growing, mission-critical niche that has massive technical/engineering moat. Cant resist have to drop everything and write this up ASAP.

Datasheets are public. This is very clean thesis. IDK how the fuck this random Japanese company made this thing but its way WAY better than anything else on the market.

The keys specs are energy density. Particularly volumetric energy density. Musashi way ahead. Higher rated voltage means you need fewer of these in series simplifying control and circuit design. Will get to that shortly.

Big drawback of Musashi solution is very high ESR. (parasitic resistance)

Again, for this application, density is by far the most important metric.

As an aside, these capacitors are extremely dangerous. Can easily kill a human.

To show why density is so important, let’s look at an appliance Musashi offers that is built around their supercapacitors.

The datasheet advertises backup time but this thing has so much more value than that. Smooths out power and load spikes.

Some of you may be wondering how capacitors rated for 3.8V can be built into a product that supports hundreds of Volts.

Let’s look at a nice TI application note I found.

Oversimplified, a control circuit needs to step down the voltage and charge a mixture of batteries and supercaps. The supercaps can be stacked in series to improve rated voltage at the cost of capacitance and efficiency due to higher ESR.

Here is another example for an ADI application note.

Efficiency of this circuit is not good because you have to step down the voltage then boost it back up. Thus, ESR of the supercaps themselves is not the most important spec. DENSITY DENSITY DENSITY. The point of these things is to have a dense energy buffer, at the cost of some efficiency.

See you this weekend for memory/DRAM/HBM project.

Welcome to a very exciting project on high-voltage power semis (SiC + GaN). This entire industry has been eating shit from EV/automotive downcycle and Chinese competition.

Whats super awesome about this space is the above two major negative factors are irrelevant to the sector going forward in my opinion.

Broadly speaking, power semis are all about tradeoffs between the following factors:

1. Footprint (how big circuit is)

2. Conversion Efficiency

3. Control complexity.

4. Switching Frequency vs Voltage (effects above three)

In EV/automotive, you can compensate for lower efficiency with a larger battery. There is enough space/footprint to make cheaper SiC parts work economically. Thus, you get a race to the bottom which we have seen.

Datacenter and power grid markets are the opposite. Every last shred of efficiency matters. Footprint is critical. You either fit in the power sidecar rack or you don’t. And due to national security and supply chain risks, Chinese parts on the USA power grid is not gona fly with Trump. You can bet the Hyperscalers who are desperately trying to prop up domestic transceiver manufactures ([LITE, AAOI, COHR] over the Chinese [Innolight/Terrahop, Eopto, Accelink]) are putting the same pressure on the power module supply-chain.

This entire market is moving from a knife fight between retards who over-built (looking at you Wolfspeed) and Chinese players with 30-40% lower cost to a quality-based pricing regime where demand is going to vastly out-strip supply by H2 2027, if not earlier.

The best part is, all the datasheets are public! Was pleasantly surprised by this as the low-voltage switching regulators tend to have private datasheets to prevent easy analysis of “who has better part”. A friend told me these high-voltage parts have public datasheets due to regulatory/safety reasons so horary for red tape for once that shit is useful.

Over 10 years ago, I got destroyed in my first upper-division undergraduate analog design class. Spent 50+ hours per week on JUST THAT ONE CLASS, practically lived in the shitty lab where we built test circuits on breadboards and simulated on PSpice. Failed the final exam because my dumbass forgot a resistor and ended up designing an amplifier that tied output to ground. TA gave me 10% on that design problem because my frequency domain analysis of transistor parasitic capacitance was correct. Got a B- (others failed harder than me) and pivoted entire life/career. That one class killed my dream of becoming a chip designer. Realized no matter how hard I tried, I could never be good at chip design. Pivoted to digital signal processing, the opposite sub-field in electrical engineering.

So… I am completely un-qualified to write about this but gona try my best anyway. It’s funny how life turns out. Can’t design circuits but I can read datasheets, play with existing simulation files, and make money trading/investing in analog semis.

Contents:

1. SiC vs GaN: The Pointless Argument

2. Tour of Sample Circuits

   1. 500V DC to 200V AC (1-phase)

   2. 200V + 200V DC to 115V AC (3-phase)

   3. 800V DC to 12V DC

   4. 800V DC to 50V DC

   5. Key Points

3. Transistor Attribute Crash Course

4. Datasheet Comparisons

   1. GaN+SiC 650V-class

   2. SiC 1200V-class

   3. SiC 1700-2000V class

   4. Wolfspeed 10KV Madness

5. Driver Integration, Protection Circuits, Buffers == VALUE

6. Multi-Sourcing, A Practical Perspective

7. EPIC OPPERTUNITY: Solid-State Transformers

8. Public Market Investment Corner

[1] SiC vs GaN: The Pointless Argument

Many companies in this world are biased and spout bullshit claims that have no technical merit.

Let’s start with this excellent slide from .

The chart itself shows the key design tradeoff between SiC and GaN.

GaN enables higher switching frequencies.

SiC enables higher voltage and power density.

Wolfspeed has no GaN exposure so they try their best to shill SiC as a better market. This is bullshit.

Conversely, Navitas is far more levered towards GaN and tries to shill that as much as possible. Also bullshit.

Finally, Navitas CEO likes to claim that it matters that they have both SiC and GaN and this is somehow an advantage. Complete bullshit.

Nobody gives a damn if one company can offer both. Designers will chose the best SiC and best GaN parts for the situation. Literally nobody cares if both parts come from the same company.

By the end of this post, you will understand:

1. The tradeoffs between SiC and GaN.

2. Why both have significant value.

3. Who has the best SiC.

4. Who has the best GaN.

5. How circuit designs enable multi-sourcing and the limits around these strategies.

You gona want exposure to both SiC and GaN.

Let’s get started!

[2] Tour of Sample Circuits

My original goal was to build some sample circuits and simulate multiple parts against each other. Very quickly realized this is not going to happen.

Simulation software for this kind of thing is called SPICE. PSpice (Cadence) is the industry standard. LTSpice (Analog Devices) is free so I am using that.

Vendors provide models for their devices. For example, here is the SPICE model for Infineon 650V-class GaN discrete MOSFETs.

The part I was trying to import has this model.

If I am too dumb to import a model, I absolutely can’t design a circuit based on YouTube tutorials.

And so, the search began for some pre-made LTSpice schematics. Found a glorious resource from ROHM semiconductor.

https://www.rohm.com/support/ltspice-circuit

Full, ready to run schematics with detailed PDF guide on how to edit the parameters. Exactly what I needed.

The rest of this section is a walkthrough of some of the ROHM sample circuits. My goal is to build your intuition before going into more technical details.

I highly encourage all of you to download LTSpice (free!) and these ROHM files and play with them yourself. It’s easy! Even a midwit boomer PM like Brad Gerstner could set this up.

https://www.analog.com/en/resources/design-tools-and-calculators/ltspice-simulator.html

[2.a] 500V DC to 200V AC (1-phase)

Let’s start with the red box. This is the PWM controller. Thing that sends the signals to control when the SiC transistors (green box) turn on/off.

Opening up the SPICE model shows this…

It’s just a bunch of hardcoded math. In the real world, more sophisticated control algorithms are sometimes needed. Depends on the ripple/stability/temperature requirements.

Blue box is just basic protection circuitry using some Schottky diodes. Prevents the transistors from frying the controller and vice-versa.

Let’s run the simulation and probe different parts of this circuit.

As you can see, voltage input (green) is perfect/flat/ideal 500V DC.

The output is 200V AC. Notice how there is ripple. This is undesirable and must be controlled within a certain tolerance depending on the application.

If the DC source was not a perfectly flat 500V, this ripple would be even worse.

Hint: the real world does not have ideal voltage sources.

[2.b] 200V + 200V DC to 115V AC (3-phase)

Here is a 3-phase DC to AC converter. You will understand what this means shortly.

Notice there are three controllers. You can build a single larger controller chip but for the purposes of managing the simulation, it’s easier to just make three small controllers.

Let’s probe the output current across the three load resistors.

Three AC signals at a 120-degree offset (slight time delay) are generated.

Probing the nodes between each pair of transistors, you can see the switching action. How the transistors turn on and off to generate a square wave.

[2.c] 800V DC to 12V DC

Now to a more interesting circuit. 800V DC direct to 12V.

See how there are two halves to this circuit, separated by inductors? This is called isolation. It’s a safety strategy.

It takes time for the output voltage to ramp to 12V target.

Zooming-in, you can see the ripple.

In this case, the ripple is only +/- 50 mV which is pretty good given the power conversion ratio. But remember… the 800V voltage source is ideal. In the real world, input ripple/noise is amplified. Output filer design is critical.

The output filtering of this schematic is quite basic. Handful of inductors and diodes.

Output filtering can become much more complex with higher-order LC filters and de-coupling capacitors.

[2.d] 800V DC to 50V DC

This one has two important concepts. Notice how the transistors on the left half are labeled “sct”, aka subcircuit. They are in fact, TWO transistors stacked on top of one another.

This is because there is too much voltage across this node for one SiC transistor to handle.

Looking at the ROHM datasheet…

It’s two 600V-class transistors shoved into one (fat) package to give a device that has 1200V rated max Vdss. Obviously there will be more parasitic resistance and you have to control two gates but hey it works. The alternative is 600V rated transistor go kaboom.

Similarly notice on the right side there are clusters of four transistors.

This setup is to get around the current limitations of the individual devices.

The design has quite a bit of overshoot at startup. 20%

Overshoot can fry your load if you don’t plan things right.

[2.e] Key Points

Remember, the point of this section was to build intuition. Here are the key takeaways you need to remember going forward.

#1 Signal quality matters.

Overshoot can fry your load device.

Ripple can de-stabilize the system, making load devices unusable.

Input noise/ripple can be amplified by the power conversion circuit.

#2 Transistors can be chained to increase rated power/current/voltage.

Voltage too high? Just stack transistors in series.

Current (or power density) too high? Just stack transistors in parallel.

THERE IS A DOWNSIDE TO THIS. CONTROL COMPLEXITY AND EFFECIENCY SUFFER FROM THESE STRATEGIES.

#3 SAFETY IS CRITICAL. THIS SHIT IS DANGEROUS.

All of these demo circuits have only the most basic protection measures. Real products need MUCH MORE protection. The consequences of failure include but are not limited to…

1. Fire

2. Death of technician

3. Frying $10M+ of downstream or upstream equipment.

[3] Transistor Attribute Crash Course

Each of the upcoming datasheets is for a discrete MOSFET. One single transistor.

Turns out, it takes at least 5 pages of charts and 2 pages worth of tables to describe one transistor.

Only some of the datasheet is useful for our purposes. (PICKING STONKS)

For this exercise, I will use an Infineon datasheet because I like their formatting the best.

At the top, they have a table with key specs. They are all at 25C die temp which is useless but that’s why we have to go deeper with the charts later. One step at a time…

Vdss is the maximum voltage across the transistor/switch. You never want to be in a situation that is close to this number so it’s more marketing. In practice, a design will ensure less than say 500V for margin of safety.

Rds_on is the parasitic resistance and the MOST IMPORATANT SPEC. When the transistor is on, it ideally should be a perfect short circuit. In reality, there is some parasitic (unwanted) resistance that directly leads to power efficiency loss and heat generation.

Qg is gate charge. This is another parasitic effect. Gate is the control pin. Unwanted capacitance at that pin means it takes longer for the transistor to switch between on/off.

Id_pulse is the maximum instantaneous current that can pass through the transistor. Like Vdss, you don’t want to be anywhere near the max for safety reasons.

Qoss and Eoss is capacitance/energy stored/dissipated by the transistor. This is bad because that energy is wasted every time you switch from on/off or vice versa. Notice how these two specs are quoted at 400V even though the transistor is rated for 650V. YOU NEVER WANT TO BE ANYWHERE NEAR MAX RATING. SAFETY SAFETY SAFETY.

All transistors have a threshold voltage (minimum voltage needed to make it start turning on) and a recommended voltage for operation.

In general, lower gate voltage requirement is better. Simplifies control circuitry design and efficiency.

Switching losses == wasted energy

As you can see from the warnings and many asterisks, a lot of factors can mess with performance. Designing quality PCB and supporting circuitry is difficult. Easy to fuck this up.

Maximum power dissipation is directly linked to temperature. This is why the numbers are 25C are useless and you have to read the charts. There is no reality in which these parts will run at 25C at nominal conditions.

Safe operating area is determined by three factors:

1. Switching speed (faster means transistor is stressed for shorter bursts so you can push it harder)

2. Voltage

3. Current

Each curve corresponds to a gate drive voltage. Remember that Infineon recommends a drive voltage of 18V for this part.

Parasitic resistance varies due to many factors, but the one we care about the most is temperature.

Also handy reference for parasitic capacitance.

[4] Datasheet Comparisons

For the purposes of this set of comparisons, I will attempt to make the playing field fair.

General Rules:

1. Only compare discrete MOSFETs. (no compound devices such as half bridge)

2. Chose the lowest Rds_on part from each vendor.

3. Group by voltage class.

4. Must be in appropriate package for the target market. (TOLT preferred)

Each section will also have a target die temperature picked somewhat arbitrarily by me. Comparisons at 25C are retarded so me picking some higher temp at random is still better.

[4.a] GaN+SiC 650V-class

GaN is currently limited to only this voltage class but vertical GaN might be real and enable GaN penetration into higher voltage classes. But for now, GaN stops here.

It took over 6 hours to make this table.

Many of the numbers are judgement calls from me staring at charts. Actual numbers in the datasheet are typically disclosed in inconstant ways or at useless conditions (25C case temp).

Quick comment on packages. TOLT is a style of package that allows for top-side cooling. Think liquid cooling of very dense power modules. TOLL (not TOLT!) is bottom side cooling where the PCB acts as a heat spreader. This is bad. Any package that does not allow for dense construction with topside cooling is categorized as “wrong”.

Let’s start with comparing GaN and SiC as a whole.

Broadly speaking, SiC can handle more power. This is expected. However, this comes at the cost of much higher parasitic and intrinsic capacitance. This means slower switching speeds, higher switching losses, and much larger inductors/capacitors/magnetics in full designs.

For 650V GaN, TI and Navitas are clearly in first place. Infineon is second place while STM has a competitive part in development but it is not ready. Once the new STM GaN part is ready, it will probably be tied with Infineon in second-place. Everyone else is far behind.

For 650V SiC, Infineon is in first place with STM is a close second place. Wolfspeed an On Semi are in a close third place. SiC world is more competitive.

I want to re-emphases a few points.

1. Both GaN and SiC can work well in the 650V class market.

2. Engineering is about tradeoffs. If anyone tells you only SiC or only GaN works in this market they are full of shit and biased.

3. It is irrelevant if one company offers both SiC and GaN. People will buy parts from multiple vendors based on quality and availability.

This brings me back to the mini-roast of Navitas CEO. Congratulations on having the worlds best GaN. Your SiC is shit. Why would anyone buy your SiC when Infineon, STM, Wolfspeed, and On Semi all have better parts?

[4.b] SiC 1200V-class

Thankfully the higher voltage we go, the fewer players there are so these tables are less painful to make.

Infineon wins with extraordinarily low Rds_on. The capacitance numbers are huge but so is the density. This thing can handle insane power in a single, compact device with proper topside cooling.

I chose 100C case temperature for comparison as a conservative setpoint. With good liquid cooling, you can hit like 80C and this crazy part can dissipate 800W of power!

Who gives a fuck that your capacitance is high. Run in slow at 0.1 MHz, make inductors bigger, only use one of these instead of like 3-4 competitor parts with significantly worse Rds_on.

Infineon crushes this category.

[4.c] SiC 1700-2000V class

Weird category. All of the place.

Infineon win via their 2000V part (the 1700 part is dogshit), Navitas second place. Everyone else dogshit.

[4.d] Wolfspeed 10KV Madness

There are no SiC transistors in the world that can handle more than 2000V. Infineon has some modules (half bridge, two transistor) that go up to 3300V but that is not a fair comparison. Remember, one of the rules of this whole analysis is discrete FET only. No half-bridge, full-bridge, or compound multi-power-transistor devices. Only control electronics allowed as an exception.

See the two power transistors? This does not count. Infineon SiC stops at 2000V under my definition.

So… let’s take a look at the Wolfspeed datasheet in detail.

Bare die is fine given how crazy this part is.

Really guys? You reaching here lol.

Remember you never want to be anywhere close to Vds_max. Let’s get a clue on what voltage Wolfspeed recommends for this part.

3000-6000V. Ok understandable. Still crazy.

Rds_on degrades… very severely against temperature. Even at a conservative 100C, you get 2x so 610 mOhm. Custom package and cooling needed to use this part. It’s gona kick out a comical amount of head in such a small footprint.

Parasitic capacitance is surprisingly good. I was expecting it to be much worse.

Switching losses are fairly insensitive to temperature.

Overall, I am quite bullish on the Wolfspeed 10KV part. It enables massive simplification of solid-state transformers and grid infrastructure. If and only if the customer designs package and cooling around this part.

Rds_on is super sensitive to temperature. You need good water cooling to keep this thing at good efficiency.

[5] Driver Integration, Protection Circuits, Buffers == VALUE

Let’s talk abut driver integration and protection circuits. SerDes me thinks “buffer” but perhaps this is the wrong analogy.

The main reason I rate TI and Navitas GaN above Infineon GaN is because of these integrated features. To understand why, let’s look at an Infineon application note on GaN driving recommendations!

Power semi circuit design is easy to fuck up. This is why all the companies have detailed (15+ page) application notes and teams of application engineers to support customers. Many designers choose parts based on customer support quality. In the low-voltage world, I know designers who prefer ADI/TI/MPS simply because the application engineers and support documentation are more helpful.

GaN transistors have very low threshold voltage. Too low. It creates control issues.

Negative gate drive voltage is required to proper operation. This makes the control circuits much more complicated. Really everyone, this is so fucking annoying lol.

Infineon tries to make your life easier by selling a custom GaN driver. Does the above schematic still look complicated? It is complicated!

Let’s compare Infineon’s solution with TI/Navitas.

TI integrates all the painful driver shit into the same package as the GaN FET. You just use simple PWM control as if this was a normal Si or SiC part.

There is the integrated negative gate voltage circuit. All of it is done for you.

Navitas has something very similar. Arguably better as they include extra protection circuity.

Integrated short-circuit protection is a great feature. I am not familiar with Miller clamps so let’s find out together what that is…

Ah so it’s just an extra transistor that that protects the gate driver by sending nasty pulses to ground. Seems similar in spirit to spamming Shockley diodes on all drive circuitry.

Anyway, my point here that I really realaaaallly want everyone to understand is integrated protection in GaN devices is very valuable.

Only TI and Navitas have both integrated protection and high-quality GaN FET. Nobody else has both.

[6] Multi-Sourcing, A Practical Perspective

Multi-sourcing is very common in power electronics world. Everyone has 2-3 sources for a particular product, sometimes 4. This is necessary for supply-chain reasons.

To understand what kind of work it takes to qualify a new part for an existing design, it is best to go through an example. Infineon has a nice SiC application note so I will use that.

These detailed guides and documents are public because the consequence of mistake is kaboom. You do not see this kind of stuff from TSMC floating on the free and open internet. :)

A LLC resonant converter consists of four parts:

1. Two strong SiC transistors.

2. A resonant tank consisting of one capacitor and two inductors.

3. A transformer+rectifier consisting of three inductors and two diodes.

4. At least one output filtering/decoupling capacitor.

I will skip 14 pages of math and go directly to what we chare about, how the MOSFET selection effects the design.

Remember, Rds_on is the most important parameter.

In general, lower is better so the design should be set up to support the least resistive transistor available. However, the way certain resonant designs work means you want a specific Rds_on to get optimal efficiency in some cases. This is why All the manufactures offer 5+ versions of the same transistor with varying Rds_on.

Designs also have an optimal switching speed. This is where GaN excels, offering higher switching frequencies than SiC and enabling a wider design space.

Multi-sourcing is not easy. A lot of math and simulations have to be re-done. And most importantly, markets which are sensitive to efficiency and footprint cannot second-source lower quality parts. EV you can just add bigger battery or spam more stages. You cant do this in datacenter. There is a fundamental shift coming to SiC+GaN world where quality matters again. Winners will have gross margin go up.

[7] EPIC OPPERTUNITY: Solid-State Transformers

Do you remember the Pytorch.power_plant_no_blow_up flag?

Meta (maintains the Pytorch ML framework open-source tool) added this funny flag a year ago because some grid operator got mad at them.

You see, datacenters are very unpleasant for the electrical grid. Say you have 100K GPUs training, each drawing 500W of power. During training, some large subset (say 20K GPU) drop down to 200W because they don’t need to run at full math speed for whatever reason. Waiting for all-reduce whatever.

That is a 6 MW load drop. Followed by a spike up later.

Power grids are not designed for this level of unhinged transient loads.

(its not the power plant that blows up… its the grid itself…)

This is a high-voltage transformer. You have probably seen some of these at some point. They come in multiple sizes.

These are surprisingly simple devices. Basically giant inductors and capacitors.

What’s nice about these is they are cheap. Basically a hunk of metal with very simple construction and effectively zero moving or active parts.

Lead time is long but its so cheap nobody cares, until now.

The alternative to traditional transformers is called solid-state transformer (SST). IDK why it is called solid-state because the traditional transformers also solid state but whatever. People have talked about this SST tech for a while. Take this 4-year old YouTube video.

You see, when a load (AI datacenter, factory, whatever) changes rapidly, it “pulls” on the grid, creating noise and back-propagating phase/voltage/current ripple. The normal transformers just pass along whatever crap the nasty tenant creates, leading to grid instability issues.

SST never really took off because it was too expensive. Nobody wanted to pay a premium for load/voltage/current/phase regulation.

I am incredibly bullish SST. Way more bullish than the SiC/GaN companies themselves.

Do you know what reactive power is?

If you have 1GW of electrical generation and 1GW of load, you are fucked. It’s not just transmission losses that lead to a gap between supply and demand, a non-trivial amount of power (reactive power) is needed to “push” the electricity through the grid and various types of loads.

All those AI datacenters having trouble getting permits and grid connections… you know why? Because the power grid operating knows that shit is gona take everything down.

It’s not just the amount of power being asked, its the type of load. Dynamic (destabilizing) load that guzzles reactive power too!

Solid-State Transformers not only help with load regulation (you don’t have to stupidly keep all GPU/ASIC at full power), it also helps reduce reactive power needs!

You are not bullish enough on SST. Unironically I believe SST opportunity is much larger and more attractive (from margin perspective) than inside datacenter power. Everyone is focused on the wrong thing. The power chips going between grid and datacenter are the real opportunity, not the Nvidia or OCP power rack.

TRADITIONAL TRANSFORMERS ARE THE ELECTRICAL-ENGINEERING EQUIVILANT OF A STONE WHEEL. ITS TIME TO UPGRADE. AI DATACENTERS ARE A MUCH STRONGER CATALIST THAN PEOPLE THINK. THE PREMIUM PRICE IS TOTALLY JUSTIFIED.

[8] Public Market Investment Corner

First, disclosures.

I have 50K waiting to go into IFX but Interactive Brokers has some stupid limit on deposits.

That 50K is going into more IFX and AIXA. Have not decided on the split yet.

I strongly believe that exposure to both GaN and SiC is desirable.

For GaN, TI and Navitas have the best parts while Infineon in second place. TI is not a pure-play so I sold out. FYI Infineon has a very recent patent case against Innoscience. Navitas and Infineon also have a cross-licensing and second-sourcing agreement.

A hedge fund friend tells me that On Semi and STM both buy GaN wafers from Innoscience which will… have problems going forward. IFX makes their own GaN wafers and Navitas is fabless using GloFo wafers. Bullish IFX and GFS. GloFo losers are not getting any meaningful SiPho volume so at least they can use cleanroom space for lower margin GaN.

On Semi has exciting vertical GaN technology but there are no public datasheets. This is just a bunch of hopes and dreams on slides. I sold out at nice 15% profit in like 2 weeks because after completing full DD, their SiC is meh and lateral GaN meh. If anyone has real technical info on vertical GaN, email me.

Infineon has a dominant position in SiC. Crush everyone in 1200V category. For 1700-2000V, Navitas is ok (Infineon still beats them) and everyone else is shit.

I believe the Wolfspeed 10KV part will play a huge roll in SST revolution. Enables drastic reduction in control complexity.

For semicap, I am now even more bullish Aixtron. Was buying for InP but they also have almost monopoly position in GaN. This is a STONK.

Finally, some wildcard picks. The companies that actually make SST are Delta Electronics and other large well-diversified, respected firms. The Vertivs and Eatons of the world.

If you want safe outperformance, go for Delta Electronics.

If you want degen shit to gamble… let me introduce you to and , two corpses.

Both of these shitcos are in the home solar market, which is fucking dead now that tax credits are gone.

You see, solar panels are high-voltage DC but your house is low-voltage AC. So each solar panel needs a DC to AC inverter and all of these “micro-inverters” need to be controlled in a safe way such that they are in the correct phase and can interface both to your house and the grid.

This is a distributed systems problem where safety is critical. The consequence of failure includes but is not limited to:

1. Dead technition

2. Fire

3. Dead/crispy customers after house burns down

4. Grid damage and lawsuit from grid operator

The real value-add of these companies is not the power circuit design itself. It is all the safety circuits and control circuits.

Remember the examples section…?

It takes only four fucking transistors to convert 500V DC to 200V AC. The hard part is making this circuit safe, linking many copies together, and controlling it all.

Enphase and Solaredge core competence is this shit. Several hedge funds have expressed doubt and I am like guys wait for the post. You will see circuit diagrams and understand what I am saying. Hey Clark, did you convince your smooth-brain boss to download LTSpice?

Placing a bunch of these things in one environmentally protected box is easier than spreading them out over a roof that is exposed to the elements.

They have a fucking 22nm logic ASIC for control! You know all those STM microcontrollers are in shortage because of optical transceiver ramp right?

Some behind-the-scenes. For weeks people have been pinging me on this crap. 18 months ago I DD both of them for unrelated reasons and determined its dogshit. After the 15th fucking person sends me these two shitcos, I finally spend some time and… its not stupid. Its hilarious.

Welcome to a recap of a very eventful earnings week. Quite a few funny charts here.

Contents:

1. SiTime to the moon.

2. AMD also to the moon.

3. ARM steps on a rake.

4. Platinum Dogshit: Still Dogshit

5. GloFo Investor Day

6. Power Semis

   1. On Semi

   2. Navitas

   3. Wolfspeed

7. Optics

   1. AAOI

   2. Lumentum

   3. Coherent

   4. Fabrinet

8. Trading Account Snapshot 5/8/2026

[1] SiTime to the moon.

Let’s start with SiTime who gets to be the thumbnail of this post.

I own some shares in long-only accounts but not enough dammit. Only around $104K worth at 398% P&L lol.

Anyway, there is this draft post that keeps getting delayed by other projects on SiTime. At some point it will be published but here is the quick explination.

1. SiTime competes with Quartz crystals.

2. SiTime gets much higher gross margins because silicon memes scales way better than cutting crystals.

3. Out of the ~10 attributes the a timing source can have, SiTime technology obliterates Quartz in 9 of them.

4. The one attribute where they lose is jitter.

   1. It used to be a massive problem.

   2. Rajesh is well aware of my existence after I sent several dozen finance people after him to ask about jitter.

   3. As of around 4 months ago, SiTime released new parts that fix the jitter issue. They went from over 130 fs jitter to ~60 fs. High quality quartz can hit 35 fs easily.

Again, have a long draft post explaining jitter, PPM sync, how SiTime fixed their jitter issue, datasheet analysis, and much more.

All you need to know for now is Quartz is fucking dead. SiTime finally did it.

Congratulations friends!

PPM SYNC PPM SYNC PPM SYNC

All timing sources have natural PPM. An offset to what the correct frequency is. This natural PPM is intrinsic to the device and drifts over time and over thermals.

SiTime has the unique ability to precisely alter intrinsic PPM using an integrated fractional PLL. Quartz guys can try to copy this strategy but the source resonator is so bad it becomes a losing battle.

This is what SerDes BER looks like against PPM in general.

The transmitter and receiver have independent reference clocks what will have some intrinsic PPM. Every SerDes design has a similar impairment mapping. Basically, if you can hit system PPM of less than +/- 20 there are significant performance gains. Otherwise, you take a hit cause the CDR thrashes trying to correct the PPM.

Rest of SiTime call boring. This is all that matters. Rajesh is trying to explain this concept and does not do a great job to be honest but dumbing down this concept for bean counters is challenging.

SiTime is uniquely positioned to deliver massive value to customers via PPM sync. Their gross margins are going so much higher. Quartz is fucking dead.

[2] AMD also to the moon.

Kinda kicking myself for not buying degen calls for earnings. CPU story was obvious but was afraid of GPU noise.

And this is what I missed. They can just print older N5 CPUs. Very high yield on the CCDs because of industry-leading chiplet strategy.

Outdated (2+ year old) AMD x86 CPUs deliver better absolute performance and performance/$ than the junk ARM themselves design (Neoverse).

If EPYC is binned well (AMD is amazing at this) they can also compete in perf/watt too. There is a shortage so none of this matters anyway lol.

[3] ARM steps on a rake.

Title inspired by this TBU tweet.

ARM has been spiking because of sympathy moves with Intel and CPU news in general but… they don’t have fabs. And as a reminder, it is only very recently they started to tape-out their own designs, moving away from pure licensing/IP model.

Turns out, they don’t have enough supply. This was very obvious but IDK someone bid the stock up and got crushed.

Translation: “We don’t have the supply.”

As a reminder, AMD has a great relationship with TSMC and their CPU architecture is so good, outdated generation on N5 (which has capacity lightening up) can be re-ramped at even higher yield and gross margins.

[4] Platinum Dogshit: Still Dogshit

Several of you have commented on why I was holding Coreweave stock. It was for a trade after talking to a particular hedge fund who will be obfuscated for privacy.

Here is how the conversation roughly went. Group call.

• Hedgie #1: What you think about Coreweaves and neos.

• Me: Recently played with Oracle calls (trade in and out). made like $10K. Still thinking about how seriously to try this trade.

• Hedgie #2: <detailed thesis on Neoclouds>

• Me: Ok well I generally agree with most of what you said so why Coreweave over Oracle? Its higher quality.

• Hedgie #2: <begins to respond>

• Hedige #3: <interrupts, shouting> LEVERAGE BAYBEEEEEE

It’s not much, but at least the number is green lol.

Stock did not move much after print and had a bad feeling so bounced before management could open their mouths on the conference call.

#riskmanagment

Let’s see what they said.

So… higher component prices are not a problem because they are passed along to the customer due to how the contract is structured… but it is a problem?

Fun start with first question. I’m guessing the rest of sell-side is gona pile into this.

Uh… does once again mean when the multi-year contract is done and a new contract is written? Or does “once again” refer to CEO re-iterating prior statement that everything is fine and higher component costs get passed through?

These answers are very confusing.

[5] GloFo Investor Day

GloFo had an investor day right after their earnings so I will cover that instead. There are only a few slides that interest me.

If you x-ray transceivers, you will see vast majority of the SiPho ones have Tower PIC. And the driver+TIA chips are designed by Semtech and fabbed by Tower too.

Overall, the slides are full of word salad with almost zero technical information. Tower has been eating your lunch guys. What is new here?

Speaking of word salads, GloFo is really trying to attach themselves to OCI. Almost everyone is using TSMC COUPE or Tower hybrid bonded solution.

As a reminder, let’s look at the comparison of ring modulator S21.

Note: Tower chart has a typo for y-axis label. Let it go guys its a dumb mistake on their part.

Many finance friends ask me how they can help given I help them for free. This is your opportunity!

I would like every single sell-side and buy-side analyst to print the above image out and ask Global Foundries management directly what the S21 of ring modulators on new SCALE platform is.

You see, the GloFo monolithic node is different from what they are now promoting in investor relations slides.

ENHANCE

It is unclear to me if this “new” SCALE platform is hybrid bonded or not. The slide clearly shows two discrete dice so this is not the fusion node. It appears GloFo finally realized their monolithic solution is un-viable after both Ayar Labs and Lightmatter fled to TSMC COUPE.

But what is replacing the monolithic fusion node that was promoted as recently as… 2.5 months ago at OFC 2026?

Show us the S21 of your new rings that “exceed OCI requirements”. I happen to be very familiar with OCI spec and would like to decide for myself.

Nothing in GloFo investor day changes my prior opinions. I continue to believe Tower Semi and TSMC have superior CPO SiPho platforms via hybrid bonding technology.

[6] Power Semis

I continue to be very excited about power semis and this is the highest priority project in the works right now. Quality takes time so sorry its gona take a while. Especially because of real life obligations and issues.

All three of the power semis companies that interest me reported this week.

[6.a] On Semi

I am very interested in the vertical GaN but all the information is generic. Basically slides and promises. If anyone knows of proper technical information please send it to me.

Bro what u talking about. Wolfspeed exists lol.

Wish there was a breakdown between SiC and GaN and other.

I checked the datasheets for the Treo parts. Mostly boring stuff that TI, ADI, and STM all sell already. To me it looks more interesting from a business perspective. My sense is ON had some spare fab capacity and wanted to make new products in a super efficient manner. Great stuff, especially given the analog shortage and price hikes. Kudos to Hassane.

Yep this is why im interested. Don’t give a shit about automotive crap. Blah blah blah 10Gbe ethernet in auto ew.

Anyone have datasheets for these V-GaN parts?

[6.b] Navitas

This is a great summary by the Navitas CEO. Helpful as I am trying to finalize which circuits to simulate.

I don’t really agree with what Navitas CEO is trying to say here. You can mix and match easily. What matters is having a technical advantage. Navitas and TI have the worlds best GaN, it seems like ON, Infineon, and Wolfspeed have the worlds best SiC but still working on that.

Nothing stops the Vertivs and Eatons of the world mixing SiC parts from one supplier with GaN parts from another supplier into the same product.

Fully agree with this though.

[6.c] Wolfspeed

We now move to the most degenerate ticker to be covered for today. Wolfspeed is a recently un-bankrupt shitco that literally has negative gross margins.

This is all I care about.

TOLT is a standard packaging format for power semis. As Navitas CEO loves to tell everyone, you need the right package to enter the AI/Datacenter market. Footprint is critical.

There is no SPICE model for the 10KV SiC part so I am trying to make my own model in LTSPICE. This is not fun and part of why the upcoming project is gona take so long.

[7] Optics

Everything down. Seems like market jitters and some pod monkies rotating. Not much news on engineering side.

[7.a] AAOI

Cursed chart lol.

As a reminder for fellow retail friends, AAOI has possibly the most hated CEO in this entire semis/AI/optics space. A large number of financial professionals despise this man lol. Stock is a hedge fund knife fight.

No company has such a legendary track record of missing expectations.

Let’s see what the excuse is this time lol. Last quarter I defended them over the qualification thing because it’s true… sometimes dumb shit with Tx FIR happens.

Before or after yield…?

Ok so what is the linewidth? Share the number. Intrinsic or effective linewidth? At 50C?

What is your RIN?

Does AAOI have decent laser capacity or are they trying to expand capacity at the same time as everyone else?

Lol.

For what it’s worth, TFC and several large Chinese players also make their own fully-custom, highly automated equipment. AAOI is not differentiated here.

Yes the die size of a higher power lasers is much higher. Need longer cavity length for reducing linewidth and charge density.

Interesting they plan to move to 6-inch AT THE END OF NEXT YEAR.

Will circle back to this in the Coherent call lol.

I agree.

Qualifying new lines takes time this is true.

Buddy 5K hour HTOL is the minimum requirement for laser reliability as defined in GR-468. There is no debate. Every single customer requires GR-468 qual.

Ultra-high-power laser is a totally different ballgame. Agree 100%.

[7.b] Lumentum

Nothing has changed. I still have the absolute highest conviction in Lumentum superior engineering via publicly disclosed linewidth and RIN data for their ultra-high-power laser for CPO. No other company dares to share this data properly.

The giant fab in Greensboro, North Carolina is a fucking death star.

This weapon of mass [competition] destruction is going to vaporize all the perceived “competitors” into a hot plasma of death.

Lumentum is so damn ahead, they are reducing the cavity length of their laser to boost production. Wupen and Hurlston have said on several earnings calls that capacity increased due to reducing/optimizing die size. THEY ARE TALKING ABOUT CAVITY LENGTH.

Reducing cavity length is dangerous because in increases charge density, leading to possible reliability/failure issues. It also inherently broadens linewidth. Lumentum is so far ahead you people don’t fucking understand what is happening.

ELSFP is massive opportunity for Lumentum. Simpler than transceiver in some ways.

Bradly speaking, a standard SiPho transceiver has the following component groups.

1. CW lasers + lenses + isolators

2. SiPho chip with modulators

3. DSP/retimer

4. Analog amplifiers (driver+TIA)

5. High-bandwidth photodiodes for Rx

A ELSFP only needs #1 and #2. And for #2 you can move from SiPho to passive glass, saving cost and allowing for lensed fiber arrays, reducing costly active algimnets.

The revenue and margins Lumentum will capture from ELS are insane. Do you still fucking doubt Hurlston’s death star?

How the hell do you have underutilized fabs? There have been what… three consecutive quarters of crippling supply/demand imbalance? Are you re-qualifying lines from scratch?

[7.c] Coherent

First, I would like to thank a random person on Twitter for pushing back against some of my initial comments. Softening the tone here but still think something suspicious is going on.

Let’s talk engineering timelines.

InP process takes 6-8 weeks. Burn-in is mandatory at 1000 hours which is 43 days.

Thus from wafer start to finished diced and packaged laser CoS, lets call it 3 months.

Integrating the laser submounts into a transceiver is very fast. Less than an hour for active alignment. I am being very pessimistic here.

Final transceiver test and burn-in lets say a month to be pessimistic.

Thus, wafer start to finished goods (tranceivers in Coherent’s case) should be 4 months at worst. However, this assumes both the InP line and tranceiver line are fully qualified already. So… I am still suspicious of the argument that timing mis-match is as big of a deal but willing to soften stance.

Still think Cohrent 6-inch InP is having serious issues. Lumentum explicitly told sell-side in multiple interviews they have no plans for 6-inch. AAOI just said 6-inch only starts TWO YEARS FROM NOW. AXTI is 1 year away from completing R&D for 6-inch wafer production, forget the timeline for qualification and production.

Coherent is first to 6-inch InP and appears to have faceplanted. Gross margins, continued revenue misses, and the fact that all major competitors and several key suppliers have not started work on 6-inch or plan to adopt 6-inch 3-4 years after Coherent tells me something is up.

There is a running joke within industry that Coherent is only yielding photodiodes on 6-inch. I did not come up with the joke but probably propagated it to a wider audiance.

There is a LOT of nuance in what is happening here.

As AAOI CEO told you (scroll up), high-power lasers are “a completely different ballgame” than traditional lower power lasers in terms of yield and manufacturing complexity.

CW lasers come in the following popular power classes:

• 10 mW

• 20 mW

• 40 mW

• 100 mW

• 250 mW

• 350+ mW

EMLs come in multiple datarates (50/100/200G) and reach categories (SR/LR/ER/FR/DR). Reach is determined by the power of the pump laser integrated into the EML die.

I suggest sell-side follow up with Coherent CEO and ask about yield of SPECIFIC CW AND EML DEVICES across 6-inch and 3-inch.

“Some” is an understatement given how many EMLs (particularly expensive 200G class) Coherent purchases from Lumentum.

All of the finance people are spotting suspicious numbers and asking about underwhelming margin expansion from 6-inch. Yield and of WHAT SPECIFIC DEVICE CLASS IN A POWER CLASS IN A SPEED CLASS matters.

It is likely all the 200G EMLs are coming from Lumentum/external and the stunted ramp of 1.6T transceivers is due to not being able to yield highest speed class EML on 6-inch.

MAYBE BECAUSE THE YIELD OF 6-INCH IS NOT GOOD FOR THE HIGHEST VALUE (100 mW+ CW, 200G EML) CLASS DEVICES.

200G VCSEL is not happening! Reliability will fail. You will never pass GR-468. 400G VCSEL is so idiotic I am frankly shocked he even dared to say something this stupid.

I will give credit to the second sentence. VCSEL based near-packaged-optics AT 100G per lane is a great solution. Coherent had a demo of their 100G PER LANE VCSEL NPO at OFC and it was excellent. Ultra low power and clean eyes with healthy SNR margin.

How are EML and SiPho transceivers same gross margin? This does not make sense, especially in an InP capacity constrained environment. SiPho should have better margins…

Do you have a yield problem with extra active alignments in SiPho transceiver versus EML?

200G VCSEL will never work in any context. This will fail reliability testing. VCSELs will fry themselves. I shall die upon this hill.

[7.d] Fabrinet

The call is boring. Skipping it.

[8] Trading Account Snapshot 5/8/2026

I de-levered and sold everything that is non-core. Have a bad feeling. Still quite levered relative to normal people and professionals lol.

Also withdrew another $50K to buy more AIXA and SOITEC in long-only (Interactive Brokers) account.

Hello everyone. Very excited to share an updated view on Cerebras. A lot has changed.

You can find the report in PDF format attached here.

CBRS_IrrationalAnalysis_v2

12.7MB ∙ PDF file

Download

Download

For this special occasion, I made this report using LaTex (TeXstudio+MiKTeX). This is what the editor looks like.

Last year Cerebras had a party at GTC which I crashed with someone else’s ticket. The food at that party was great by the way. Anyway, they had these fake gold “challenge coins” that say “In fast inference we trust.”

Chucked one of these coins somewhere and had to search my disaster zone of an apartment but found it. Thing has oxidized or something.

In a way, this stupid partially corroded coin is a metaphor for the company. The original goal of training is dead, tarnished by years of failure. But the underlying technological foundation is solid and can be re-used for ultra-high-speed inference.

An absurd, almost comical chain of events packaged into a tacky souvenir.

Feel like this is a suitable thumbnail.

Enjoy!

Hello and welcome to a general note on many topics. Only brief updates on each name.

First, trading account update.

The bad news is I have approximately $88K worth of options that are going to zero tomorrow.

The good news is everything else did pretty well.

As you can see, I have lost a small fortune on idiotic options plays THIS year. Literally in the last 4 months.

~$220K on puts while trying to hedge the dumbest war in history.

~$230K on calls trying to fight epic multiple contraction and general poor timing.

(to be clear I am still up ~$110K on Nvidia in the trading account and up ~$240K on Nvidia in long-only accounts)

I am rather disappointed in myself. Don’t get me wrong, I am thankful for the gains but the insane epic fails are learning opportunities. My philosophy is to aggressively shit on myself (internal monologue/thoughts) when serious mistakes happen to make sure I learn. The most dangerous behavior is to only focus on the wins and ignore your mistakes. I mentally track all mistakes greater than $20K and review them on a weekly basis.

Some random bull on Twitter has pissed me off enough to share some more information about my investment performance from September 2022 until present date.

The trading account (Webull) was created on February 28th, 2022. Initially I only had like $5K deposited.

In September 2022, I had roughly $120K worth of RSU+ESPP. Decided to liquidate all of it at around $135/share and take my future into my own hands. There are reasons why I harbor a personal hatred towards Qualcomm management. You could say I saw the AI boom coming, tried to tell them what they were doing wrong, and they did not listen.

You know why my average price for is $13.9/share? Because I sold all my at 135 and bought Nvidia at 130, 125, 121, 119, then ran out of money. Then Nvidia had a 10:1 split. Some of that money also went from ETRADE QCOM STOCK PLAN to Webull to finally fund the trading account.

With around $150K starting capital ($30K savings, $120K proceeds from liquidating QCOM) and over 3.5 years around $150K incremental/additional savings/deposits from dayjob cashflows, I have arrived at ~$2.7M in net worth AFTER PAYING TAXES.

I have since withdrawn far more than I ever deposited (across all accounts) just to pay 2025 taxes.

Qualcomm is trading at $177/share right now after a bullshit earnings. That is a 31% gain from September 2022 to April 2026.

My trading account gains over the same period is over 2000%.

My long only accounts in aggregate are up over 350%.

Qualcomm bulls, why don’t you shut the fuck up and show me your P&L?

Maybe I know more about semiconductors than you?

Contents:

1. Intel 18AP Update

2. Qualcomm Earnings

3. Analog/Power Semis

4. Semicap

5. Optics

6. My Mistakes and Near-Term Investment Plans

7. Upcoming Content

[1] Intel 18AP Update

was kind enough to share some conference paper updates on Twitter and one of them really caught my eye.

Intel 18A has dogshit process variation. Everyone in industry who touched the PDK knows this. The ongoing yield issues that INTEL MANAGMENT ADMITTED TO OVER A YEAR AFTER I STARTED SCREAMING 18A PARAMETRIC YIELD WILL BE SHIT are further evidence of this.

30% tightening of skew corners is huge. If true, Intel 18AP will be competitive with TSMC N3P.

Of course, conference papers are bullshit but even if you cut the numbers/claims in half you get a viable logic note comparable to TSMC N4 (not N4P) in PPA when logic is under a crippling shortage.

Intel is comically undervalued. I do not think people understand what this skew corner tightening means. The stock spiked today because of some SEC filing that had a bullet point on Google pre-paying Intel $1B in cash for capacity.

I AM SCREAMING THIS AT YOU. INTEL NEEDED MORE TIME. 18A ABSOLUTLY FUCKED UP DISASTER BECAUSE THEY WERE INEXPERIENCED AND RAN OUT OF TIME AND CHINA BLOCKED TOWER MERGER. I HAVE ALWAYS HELD THE POSITION THAT INTEL MUST SURVIVE UNTIL 2027 TO GET 18AP WORKING IN VOLUME FOR EXTERNAL CUSTOMERS. THEY HAVE MADE IT. FINANCE FRIENDS, YOU ARE NOT BULLISH ENOUGH INTC.

18AP IS WHAT 18A SHOULD HAVE BEEN AND ITS GOING TO BE FUCKING AMAZING FOR INTEL AND AMERICA.

[2] Qualcomm Earnings

Let’s start with this slide.

There is no way this is correct. I refuse to believe the memory crisis causes smartphone (especially Android, especially Chinese Android) to bottom next quarter.

Other parts of the call I am willing to compromise and throw a bone to Cristiano. Not this. Absolutely no fucking way smartphone bottoms next quarter. Total bullshit.

Mac Mini’s are sold out and your market share in PC is well under 1% still.

Several have pinged me on what my guess is for this custom silicon comment.

Best guess (~70% confident) is an optical DSP for tranceiver or active optical cable. Alphawave is one of the few companies with viable (well semi-viable) 112G SerDes on Samsung SF4X. Giving the timing, the custom silicon has to be an IO-heavy chip like optical DSP or AEC chip or some other retimer. Maybe a PCIe switch? Front-end NIC?

Ah yes pumping 6G. After 5G completely whiffed on basically every promise and “new use case/market”, we gotta push a new generation of wireless technology nobody asked for or needs.

Memory prices still going up. Oil price way up and hurting Asia the most. Yes surely there won’t be demand destruction on discretionally purchases such as high-end smartphones. Clown.

All the important people who designed that CPU microarchitecture/core left to form a new startup.

I will admit that this is a huge opportunity for Qualcomm IF THEY EXECUTE. Need to remind everyone that this is datacenter CPU attempt #3. Attempts #1 and #2 died in 2018 and 2022 respectively.

One key benefit is the CPU shortage is so bad that the bar is very low. This datacenter CPU from Qualcomm just needs to function without any obvious problems. Qualcomm has wafer capacity (from imploding smartphone market) that can be shifted to datacenter CPU.

ARM does not have the wafers.

AMD does nto have the wafers.

Intel might have some wafers as 18A yield improves but its tiny compared to what Qualcomm can bring to a starved market.

I concede this is bullish for Qualcomm but do not believe it is enough to deal with the impending implosion of core business due to memory chaos and Apple legal war risk in March 2027.