That is Jensen Huang in March, working the crowd at the Nebius booth at GTC, telling the company’s CRO that “Nebius will take care of you.” Nebius posted the clip with its own two-word caption underneath, “We will.”

On Tuesday, at Nebius’s first Inflection forum in San Francisco, I watched what that promise looks like as a business model. The product story was agents. The investment story was duration.

The market already understands the first neocloud species: CoreWeave, the contracted utility. Borrow heavily, lock in long contracts, satisfy lenders, scale with NVIDIA’s roadmap.

Nebius is trying to be the second species: the merchant generator. Fund with more equity, customer prepayments, backstop contracts, and converts; avoid five-year price locks; sell scarce GPU capacity short into a rising market.

Same GPU shortage. Opposite duration bet.

CoreWeave is a contracted utility. Nebius is a merchant generator.

The market color I keep replaying came out of the hallway. I posted it Tuesday evening

I heard this from a credible source I cannot name. I am not treating hallway color as a signed contract. I am treating it as a live price signal from people close enough to the shortage to know where the bids are. The important part is the structure: premium pricing, short duration, no spare capacity, and buyers still taking the capacity. That is the merchant book in one anecdote.

’s Sources heard the same market at the same event, with a number attached: Google reportedly paying SpaceX $920 million a month for Blackwell capacity, a high premium on an effectively 90-day rolling commitment.

The hallway quote is not the thesis by itself. It is the price signal.

Below the paywall, I’ll walk through the actual underwriting question: whether Nebius has built a merchant GPU book that can reprice into scarcity, or whether it is just another capital-hungry GPU landlord arriving before the next supply wave.

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“My job is not to stay independent. My job is to do whatever we can to create the maximum value.”

That was Gregor van Issum, Wolfspeed’s CFO, on a call with me last Friday afternoon. The man running the balance sheet of the only fully-built 200mm silicon carbide device fab on US soil told me, unprompted, that maximizing value is the only mandate and independence is one option among several. He then pulled up his notes and walked me through numbers I have not seen in a published model on this name.

I have spent three weeks underwriting Wolfspeed as an asset-vs-replacement-cost mispricing in The Watt Tax. The call did not soften that frame. It hardened it.

Behind the paywall, in the CFO’s own words: the exact dollar-per-megawatt SiC content for the 800V rack and the next generation up (the number I have not found in a published sell-side model), cross-checked against the BofA Global Research AI power semi model Vivek Arya published this week; why Wolfspeed is already printing data-center revenue at roughly 10 percent of the company while the eight named cohort suppliers BofA tracks sit at zero in CY25; the five markers from the call that establish this is a legitimate competitor with relationships and shipping product, not a bankrupt comeback story; the real Mohawk Valley utilization figure and why it is the bull case; the Apollo step-up clock that triggers in June and why Gregor will not let it set his refi timeline; the on-the-record signal that a competitor “valued far beyond us” is infringing Wolfspeed’s IP; the cleanest way this trade breaks and what I am watching; and how I am sized. This is the work. If you want the number, step inside.

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Two quick notes. This explainer is free. BEP Research just crossed 3,000 subscribers, and I’m marking the milestone by taking it out from behind the paywall. I also built an interactive version so you can watch a single link flap stall a GPU cluster in real time. If it’s useful, a share is the best thanks.

What a “Flap” Actually Is, in Plain English

A “link flap” is a network connection that keeps dropping and reconnecting. On a laptop, it is the flaky Wi-Fi blip that makes a video call freeze for a second. Annoying, not catastrophic. The reason it matters for AI is that an AI training cluster is the opposite of a laptop: it is one hundred thousand GPUs that all have to stay in perfect lockstep.

Here is the mechanism, and it is the whole piece in one paragraph. Training a large model means the GPUs repeatedly do a synchronized step called an all-reduce, where every chip shares its partial result with every other chip and waits for everyone before moving on. It is a group operation. One slow runner stalls the entire group. So when a single optical link between two switches flaps, even for a moment, the GPUs that depend on that link fall out of sync, the collective operation stalls or restarts, and thousands of otherwise-healthy GPUs sit idle waiting. The flap is local. The damage is cluster-wide.

Now scale that to the part that makes it an investment story rather than an engineering footnote. The component most likely to flap is the laser inside a commodity optical module, also called a transceiver, the part that turns electrical signals into light and back. Lasers are the least reliable, most thermally sensitive, most failure-prone element in the link. As clusters grow toward gigawatt-class power draw and the link count per cluster explodes, the math gets ugly fast: more links, each with a small flap probability, means more flaps per hour, which means more idle GPU time. Credo CEO Bill Brennan has said publicly that one customer was losing 20 to 30 percent of its productivity to link flaps before deploying the Zero-Flap approach. At hyperscale, that is the gap between the fleet a customer paid for and the fleet it can actually use. Reliability here is not a feature. It is the limiting factor on usable compute.

This is the same point I made when Credo first preannounced its blowout quarter. As I wrote in Credo Just Proved the Optical Thesis: “One hyperscaler came to Credo because they were losing 20–30% of their uptime fighting optical link flaps.” That was framed then as a copper-versus-optics story. The Zero-Flap optical line is the same reliability philosophy, pushed out to the optical distances where copper physically cannot reach.

▶ See it in motion: I built an interactive simulation. Toggle commodity vs Zero-Flap optics and watch a single link flap stall the cluster and idle the GPUs in real time. tools.bepresearch.com/zero-flap

How Zero-Flap Works: Three Layers, One North Star

Zero-Flap attacks instability on three layers at once, which is exactly why Credo calls it a system and not a component. Start with what every optical link has to do: convert an electrical signal to light using a laser, push it down a glass fiber, and convert it back using a photodetector, with a digital signal processor (DSP, the chip that cleans up and reconstructs the signal) on each end. Every one of those steps is a place a link can degrade. Zero-Flap engineers against degradation at all three of the layers it can control.

1. Hardware: fewer lasers, fewer failure points. Through the Dust Photonics acquisition, Credo brings in silicon photonics, an approach that integrates much of the optical function onto a silicon chip and uses substantially fewer lasers per link. Fewer lasers means fewer of the single most failure-prone parts, better power and cost per link, and less exposure to the industry-wide laser supply shortage. Paired with an optical DSP tuned specifically for link stability rather than raw throughput, the hardware is built to flap less in the first place.

2. Software: catch the flap before it happens. Credo’s “PILOT” software, integrated at the switch level through the switch maker’s software development kit (SDK), continuously reads link-health telemetry, the bit error rates, signal-quality histograms, and laser-degradation signals coming off each module. Think of it as the check-engine light for the optical link: it reads the signals that precede a failure and autonomously detects and mitigates an instability condition before the link actually drops the cluster. Prevention, not cleanup.

3. Integration: own more of the stack, see more of the link. Because Credo controls both the DSP and, through the silicon-photonics intellectual property, the photonic integrated circuit (PIC, the chip where the light is generated and routed), it gets tighter DSP-to-PIC integration than a vendor selling one piece. Tighter integration means richer telemetry, deeper diagnostics, and system-level optimization that a component supplier stitching together someone else’s parts simply cannot match.

The result management claims is meaningful improvement in network reliability, faster time to a stable cluster, and longer uptime. This is the same mechanism I flagged the day the Q3 call landed. As I wrote in Credo’s Q3 Call Answered Every Question, what makes Zero-Flap a moat is the system integration delivering “autonomous detection and mitigation of link flap events before they impact the cluster.” The defensible part of a system like this is the hardware integration beneath it, far more than any single component, and that distinction is what the bear case below turns on.

Why It Matters Commercially: Three-Digit ASPs Change the Mix

The reason Zero-Flap is the highest-leverage part of the Credo story is that it sells a system, not a part, and systems capture more dollars per link. On the Q4 FY26 call, Credo’s CFO framed the economics plainly in Q&A: Zero-Flap optics carries three-digit average selling prices (ASPs), versus two-digit ASPs for the discrete building blocks, the standalone optical DSP and the photonic integrated circuit. The same physical link, sold as an engineered reliability solution instead of a bag of components, captures roughly an order of magnitude more revenue. That is the whole commercial argument in one ratio.

Stack that ASP onto the volume story and you get management’s own math: as Zero-Flap ramps, it becomes the largest revenue contributor inside Credo’s optical portfolio. By management’s framing on the Q4 call, which is worth confirming against the filing rather than the auto-generated transcript, Zero-Flap is guided above $100M in FY27 as one of three optical legs each above $100M, for a total optical business above $600M. The discrete DSP and PIC legs ramp more linearly. Zero-Flap is the hockey stick, steep and back-half FY27 and FY28 weighted, because it is gated on hyperscaler qualifications converting to volume rather than on smooth quarterly shipments.

That hockey-stick shape is the source of both the upside and the risk, and I will be precise about both. The upside: an order-of-magnitude ASP advantage on the fastest-growing optical leg, ramping into a reliability problem that gets worse, not better, as clusters scale. The risk lives in the back-half timing, which is the bear case below.

The Strategic Option: A Direct Path to Co-Packaged Optics

The Dust silicon-photonics roadmap is the part of Zero-Flap the consensus model mostly overlooks, and it is low-cost optionality on the next architecture. The same silicon-photonics intellectual property that lets Credo use fewer lasers today scales across 800G, 1.6T, and a path to 3.2T network speeds. That roadmap is also the direct on-ramp to co-packaged optics (CPO) and near-packaged optics (NPO), the architectures where the optics move onto or next to the switch chip itself, with initial revenue around FY2028.

This is where Zero-Flap becomes more than a product line and starts to look like a position in the next architectural transition. The physics is the lane-speed jump from 100G to 200G per lane, which makes the laser the binding, reliability-limited component and reshuffles who captures the margin. Zero-Flap is Credo’s answer to that physics from a different layer: instead of competing to build the most reliable laser, it engineers a link that needs fewer of them. As the industry moves toward CPO, the company that already owns the DSP-to-photonics integration and the reliability software is positioned to participate rather than be displaced.

Why It Matters Technically: Reliability Becomes the Binding Constraint

As AI clusters scale toward gigawatt-class power and denser architectures, even isolated link instabilities stop being a tail risk and become the dominant driver of cluster availability. The variables that matter at that scale, cluster breakup time, GPU utilization, overall system availability, are all downstream of link reliability. Add more links and the aggregate flap rate rises. Pack them denser and thermal stress rises, which is exactly the condition lasers hate. The reliability problem does not get diluted by scale. It compounds with it. Credo calls reliability its “North Star,” and at gigawatt scale that label describes the binding constraint rather than dressing it up.

This reframes what Credo actually is. For a year the consensus model has treated Credo as an active-electrical-cable (AEC) company, a copper interconnect supplier, defending a niche against the optical transition. Zero-Flap inverts that. Credo is now selling optical transceivers directly, as a system-level reliability product, moving up from a SerDes and DSP and AEC supplier into the optical TAM long dominated by Coherent, Lumentum, and the merchant transceiver vendors. The product the market skips in the model is the one that changes what the company is.

The Bear Case

Three risks would break this thesis, and I am ranking them by what changes the conclusion versus what only changes the magnitude.

1. The reliability claims are management-asserted, not independently benchmarked. “Zero-flap” is a marketing term. The reliability and autonomous-mitigation claims come from Credo, not from a neutral third party with published field data across multiple hyperscalers. One number deserves special care: the often-quoted 1000x reliability figure belongs to Credo’s copper AECs measured against laser-based optical modules, and there is no comparable independently published figure for the Zero-Flap optical line itself, so do not carry it across. Optical reliability products live or die on the first deployment year of real-world data, and the high-ASP optical line is barely into that window. If early field data disappoints at a major customer, the system-moat story compresses fast and the stock reverts to being priced as an AEC incumbent with an optical side project. This is the risk that would change the direction of the thesis, not just the slope. It is also the risk I flagged when I corrected my own Credo view in Credo Was the Wrong Question: the Zero-Flap ramp is real, but it is a concentrated bet on one product line through the first year of field proof.

2. The high-ASP ramp is the latest, least-proven, most supply-chain-dependent leg. The hockey-stick shape means the execution risk is concentrated in the back half of FY27 and into FY28. A hockey stick that does not bend on schedule is just a flat line that disappointed. This one depends on qualification timelines holding, additional hyperscalers signing on, and the silicon-photonics supply chain delivering into a known laser shortage. This risk changes the slope and the timing, not the direction, but in a name where the ramp is the whole story, slope is most of the value.

3. Optics is a far more competitive arena than AECs, and software-defined reliability is hard to defend. In copper AECs Credo holds a dominant share. In optics it is the entrant against Coherent, Lumentum, Marvell, Broadcom, and the merchant transceiver and DSP vendors, all entrenched. Three-digit ASPs are an invitation to competition, not a moat by themselves. And the software layer, the part Credo leans on hardest as the differentiator, is exactly the kind of telemetry-and-SDK function a large hyperscaler could choose to build in-house. If the customers who most need Zero-Flap decide reliability software is something they own rather than buy, the moat thins from the most valuable end first.

So What?

Stop reading Zero-Flap as a marketing name and start reading it as the answer to the question the whole AI buildout is converging on: how do you keep a hundred-thousand-GPU cluster usefully online when the single most failure-prone part, the laser, sits in every link and the link count is going parabolic? Network reliability has quietly become the binding constraint on usable compute, the same way memory bandwidth and power density became binding constraints before it. Zero-Flap is the only optical product engineered, in hardware and software together, to attack that constraint directly.

For Credo specifically, that is why this one product line is the highest-leverage part of the story. It carries the richest ASPs, it ramps into a problem that worsens with scale, and on management’s own math it becomes the largest leg of the optical business and cheap optionality on the co-packaged-optics transition. The catch is price: even after its post-earnings drop Credo trades around 32 times trailing sales, a multiple that already capitalizes much of this optical optionality, which is why the proof matters more than the next print. I hold Credo, and Zero-Flap is the reason I read it as a multi-product optical company now rather than the copper incumbent it was a year ago. What I am watching is the first year of independent field-reliability data from the hyperscaler deployments, because that is what turns a management claim into a moat.

The market is modeling the company Credo was.

The product it skips is the one that says what Credo is becoming.

Read the reliability line, not the AEC line.

Coming Up

A follow-up deep dive on the Dust silicon-photonics roadmap and the path to co-packaged optics is in motion, pending a conversation with Credo’s optical leadership on the qualification pipeline beyond the anchor hyperscaler and the FY2028 CPO timeline. I will also be tracking the next two optical earnings prints from Lumentum and Coherent for the laser-supply read-through that sits underneath every Zero-Flap link. Paid subscribers get the optical-leadership conversation first.

Related research: The Great Photonic Divergence (why the 100G-to-200G lane jump makes the laser the binding, reliability-limited component and reshuffles the margin).

Disclosure: The author holds positions in NVDA, BE, LITE, CRDO, TSEM, LSCC, ORCL 2027 Calls, and ALAB. This is not investment advice.

Read the Two Lines Brennan Buried, Not the Headline Number

I’ve been pretty busy the last few days from GTC Taipei to Credo Earnings. Excited to be up in SF next week for the Nebius inflection event. Give me a shout if you would like to meet up.

I read the earnings release and listened to the call. My biggest takeaway: read the 1.6T transition exchange before you read the revenue line.

When Brennan was asked about 200G-per-lane signaling, he said FY27 revenue tied to that transition will still be relatively light because the industry is not there yet. He even added, almost as a throwaway, that there is always a rumor about delays.

On the optical DSP side, he went further. Yes, Credo has several customer programs. But he also admitted Credo does not ultimately control when those transceivers actually go to market.

That matters. On his own print day, the CEO effectively put the highest-ASP transition in Credo’s roadmap on someone else’s calendar.

The number on the tape was excellent. Revenue of $437 million was up 157 percent year over year, at a non-GAAP gross margin of 68.3 percent. Non-GAAP EPS of $1.16 cleared the roughly $1.03 the Street was carrying; GAAP EPS was $0.88. Full-year FY26 revenue tripled to about $1.34 billion, and non-GAAP net income rose roughly fivefold to about $662 million. Management then guided Q1 FY27 to $465 to $475 million and framed the full year as more than 80 percent revenue growth, with non-GAAP operating expenses growing roughly half that fast and non-GAAP net margin held near 50 percent. The operating leverage is real. By every headline metric, this re-rates a stock higher.

It re-rated lower, by roughly 12 percent. Part of the reason is mechanical and unforgiving. The $437 million beat the published consensus near $432 million but missed the buy-side whisper closer to $440 million. For most stocks a few million against an unofficial number is noise. For a stock that went into the print near 52-week highs at roughly 41 times trailing sales and about 127 times GAAP earnings, it is not. That is the gap between perfection and merely excellent, and a perfection multiple does not survive merely excellent.

Three forces hit the stock at once, and they are worth separating because only one is about Credo. It had run up into the print. Capital was rotating out of data-center-capex names and into beaten-down software the same week, a positioning move that does not care what Credo reported. Underneath both sat the company-specific repricing: the quality of the beat. The first two are market structure and they pass. The third is the one that should change how you underwrite the name, because when a company beats, raises, and falls, the market is telling you the numbers were already in the stock and that something the numbers do not fix is now the binding constraint on the multiple.

The market did not reprice the size of the beat. It repriced the quality of it.

Quality has two pillars here, and both sat under the revenue ramp the whole time the line was tripling. The first is who: in fiscal 2026, two customers at roughly 39 percent and 32 percent of revenue, three hyperscalers at roughly 88 percent. The second is when: the FY27 inflection that justifies the forward multiple is back-half-and-FY28 weighted, and management openly says it does not set the clock. Concentration is the direction risk. Timing is the slope risk. Together they are the discount the market just attached to a demand story it otherwise confirmed.

Pillar One: The Beat Did Not Dilute the Customer List

A flawless quarter does not reduce concentration, and concentration is the risk that went unpriced while the revenue line tripled. In fiscal 2026, two customers were roughly 39 percent and 32 percent of revenue, and three hyperscalers were roughly 88 percent of the total. Credo went into the print near 52-week highs, at roughly 41 times trailing sales, on a multiple that needed a flawless quarter to hold. It got one. The multiple still could not hold, because a beat-and-raise cannot dilute the customer list, and the customer list is what a perfection multiple was quietly ignoring.

This is also where the April bear case and this print part company. In April, the Credo bear was architectural: that co-packaged optics would kill copper and run the AEC business over. That case was answerable from NVIDIA’s own roadmap. As I wrote in Credo Was the Wrong Question: “the entire bear case rested on a timeline assumption that does not match NVIDIA’s own disclosed plan of record.” That was true of the copper-versus-optics bear, and copper stays inside the rack through at least 2028. It is not true of the concentration bear. Customer concentration is not a timeline assumption that resolves with the next roadmap slide. It is a structural feature of the business, and the market just decided to start charging for it.

It also tests one of my own prior reads. Three months ago in Credo’s Q3 Call Answered Every Question, I flagged the same top-two shape, largest customer at 39 percent and second at 32 percent, and called the trend improving fast off the prior 86 percent single-customer base. The improvement is real and directional. But landing at roughly 88 percent across three hyperscalers is not the diversified base a perfection multiple assumes. The direction was right. The level is still the live bear. That is the gap between the demand being good and the equity being cheap.

Behind the paywall: why the FY27 optical guide is a forward promise and not booked revenue; the two-path 1.6T architecture math and what each path pays Credo per port; why the highest-ASP optical leg is also the latest and least proven; how the Weaver gearbox just intersected the BEP memory thesis on a named customer; the emerging FY28 stack the multiple is paying for early; the three ranked bears that would change the position; and where I am holding CRDO.

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The Slide Said “A New Beginning.” The Market Read a Dev Box.

I was up last night watching GTC Taiwan and the most important thing was not a chip. It was a slide that read “A New Line. A New Beginning,” followed by “NVIDIA and Microsoft Reinvent PC, Powered by RTX Spark.” Read the second line again. Not “accelerate.” Not “enhance.” Reinvent. And the partner is Microsoft, the company that has owned the Windows desktop for forty years and just agreed to redefine what runs under it.

The market saw a developer workstation. The structural read is different: NVIDIA put a token factory on the client. The specs are not a spec bump. RTX Spark ships a Blackwell RTX GPU at one petaflop of FP4 AI performance, a custom 20-core Grace CPU built with MediaTek, and 128 GB of unified memory running at 600 GB/s over NVLink C2C, with the full NVIDIA stack on top: CUDA, TensorRT, NVFP4, RTX ray tracing, DLSS. A petaflop of inference on a desk, with an orchestrating CPU and a GPU minting tokens, both coherent on one memory pool.

That is the reframe this piece carries: the Edge Token Factory. Every datacenter GPU is already a token-minting asset. RTX Spark makes the desk one too. And the analogy to hold in your head is the right one: a regular PC is the new flip phone, and an agentic PC is the smartphone moment for enterprise compute. Local models, on-device agents, AI orchestration at the edge. Not a better version of the same device. A different category that eats the old one’s job. The demand event this triggers is not primarily a consumer wave. It is a corporate one. Jensen did not launch a product line at GTC Taiwan. He lit the fuse on an enterprise PC refresh supercycle, the kind of multi-year IT fleet-replacement wave that fires once the new device becomes how work gets done. The machine that runs local agents is not the machine sitting on the corporate fleet today, and the moment local agents become how knowledge work gets done, every box in that fleet is obsolete inventory waiting to be replaced. That is the mechanism that turns the full x86 socket from a contingent maybe into the base case: not consumers re-buying, but IT departments re-fleeting.

RTX Spark Answers the Gap I Flagged in January

In January I argued the memory wall has two sides, and that NVIDIA owned the datacenter while Apple was quietly positioning to own the edge. The reason was bandwidth, and I named the exact part that fell short.

As I wrote in The Other Memory Wall: Why Clawdbot Is Selling Mac Minis: “DGX Spark announcement at CES 2025 shows they see the edge opportunity. But LPDDR5X at 273GB/s can’t match Apple’s unified memory efficiency for single-stream inference.” That line is the one this product tests. I made bandwidth the yardstick of the edge fight in January, and on that yardstick NVIDIA’s edge part was not yet competitive.

RTX Spark is the answer to my own critique. 600 GB/s of NVLink C2C unified memory is a direct response to the 273 GB/s gap I flagged. The architecture that beat NVIDIA at the edge was unified memory bandwidth. NVIDIA just shipped unified memory bandwidth.

Now the honest part, because the table later in this piece contains a number that complicates the victory lap. Apple did not stand still. Apple’s current top desktop part, the M3 Ultra, runs roughly 819 GB/s of unified memory bandwidth, still ahead of Spark’s 600 on the raw number. NVIDIA closed the gap it was behind on in January. It did not leapfrog the incumbent’s flagship on bandwidth alone. Bandwidth was my chosen yardstick in January, so let me be straight about why the yardstick legitimately changes now: once a coherent memory architecture clears the threshold where the model fits and streams without a PCIe tax, marginal bandwidth above that line matters less than what orchestrates on top of it. NVIDIA is now in that regime. The fight moves off raw bandwidth and onto the two axes where NVIDIA is strongest: the orchestration CPU and the software stack. I am choosing those axes after conceding the one I lost, and I want that on the record.

Why It Is a Category, Not a Spec Bump: The Orchestration Layer Comes to the Desk

The reframe is the orchestration layer, and that is what makes RTX Spark a category and not a workstation. An agentic machine is not one that generates tokens faster. It is one that can generate tokens AND decide what to do with them, locally, in a loop, without a round trip to the cloud.

The cleanest articulation of why that is a platform shift came from Jensen himself in the GTC Taiwan keynote framing, and it is the anchor for the whole category claim. He likened running a local model on the PC to a DirectX plugin: the LLM becomes a system-level runtime that the OS and every application calls into, the way DirectX abstracted GPU hardware for games in the 1990s so that no game had to talk to the silicon directly. That is the tell. The agentic PC is not a faster PC. It is a PC where the local model is a first-class OS service, a DirectX for AI, an inference runtime layer that every app calls rather than a feature that one app bolts on. A spec bump makes the same software run faster. A new runtime layer changes what software is. That is why this is a platform shift and not a faster box, and it is exactly why the partner is Microsoft, the company that owns the OS that has to expose that runtime.

The division of labor is the whole point, and RTX Spark puts both halves on one board. The Blackwell GPU mints the tokens. The 20-core Grace CPU orchestrates, running local Nemotron models that route, schedule, and drive your agents through the read-execute-debug-rerun loop that an agent actually is. Token generation is the easy half. Deciding what to do with the tokens, in a tight local loop with no cloud round trip, is the half that needs a CPU sitting on the same coherent memory pool. The unified memory is what lets the two halves work without a PCIe tax between them.

And here is the genuinely hard part, the feat the bear case turns on. The entire stack, Windows, the CUDA and inference runtime, and the local model layer that becomes the DirectX-for-AI service, has to run on a custom ARM-based Grace core, not on x86. Getting all of it to work on an ARM core is the engineering bet underneath the product, and it is the same gauntlet that has humbled every prior challenger: making the full Windows application ecosystem run well on ARM is precisely what tripped Qualcomm’s Snapdragon X. NVIDIA and Microsoft co-engineering Windows-on-Arm and clearing that bar is the bull point. The fact that it is the same Windows-on-Arm compatibility gauntlet that has defeated everyone before is the bear point. Both are true, and which one wins is the open question this product runs into.

This is not the author’s hand-wave. The orchestration half has a sourced spec. Nemotron 3 Nano posts a 99.2 percent instruction-following score and ships purpose-built for multi-agent tool-calling, the exact workload a local orchestrator runs, with deployment paths like SGLang built for multi-agent tool-calling rather than single-shot chat. And the demand shape is on the record. As Stuart Pitts told me at GTC in The Agentic CPU: “Agentic systems use up to 15 times more tokens than single-purpose AI agents. And they’ve also gotta be fast.” Fifteen times the tokens means fifteen times the orchestration overhead, and that overhead is CPU work sitting between every GPU call. RTX Spark is the first client part to put both that orchestrator and a token-minting GPU on one coherent memory pool, which is why the category claim is architectural, not marketing.

This is the same socket logic I traced up the rack in The Last x86 Island, now reaching the desk. In the datacenter, NVIDIA moved the head-node CPU in-house with Vera, taking the last merchant socket it did not already own. On the desk, the custom Grace-plus-MediaTek part does the same job to the same incumbent: NVIDIA is no longer assuming the x86 socket under this class of Windows machine. That is the bet Apple already won on the Mac, and the one Qualcomm has so far lost on Windows. Which precedent RTX Spark follows is the open question, not a settled one.

There is a wrinkle in this story worth naming honestly, because it is the kind of thing a sharp reader catches and it complicates the clean “Jensen declared death on x86” read. NVIDIA recently took a multibillion-dollar equity stake in Intel. So the company shipping the custom ARM part that routes around Intel’s socket is, at the same time, one of Intel’s shareholders. Read it one of two ways. The charitable read is a hedge: NVIDIA owns upside on both the x86 incumbency surviving AND on its own disruption of it, which is exactly the position a company takes when it is not certain how fast the socket moves. The sharper read is a tell: even the disruptor is insuring against its own thesis, which tells you NVIDIA does not model the x86 socket collapsing overnight either. Both reads point the same direction. The socket is moving, but on a clock measured in upgrade cycles, not quarters, and NVIDIA has placed money on both sides of how fast.

The roadmap is the durability evidence, and it is the strongest counter to “niche dev box.” This is not a one-off. NVIDIA showed three generations of agentic personal computing: Grace Blackwell Spark in 2026, Vera Rubin Spark on LPDDR6 in 2027 to 2028, and Rosa Feynman Spark in 2029 to 2030, with a DGX Station for Windows alongside RTX Spark at each generation. A company does not lay out a three-generation client roadmap for a science project. It lays one out for a platform. The caveat that keeps this honest: a roadmap is stated intent, not destiny. Intel and Qualcomm have both shown multi-generation client roadmaps that the ecosystem never converted. The roadmap raises the floor on NVIDIA’s seriousness; it does not settle the attach rate.

Below the line is the work itself, not a promise of it: the reconciled TAM, the defensible 30 to 50 million premium beachhead as the base case and the full 260 to 280 million x86 socket as a contingent expansion scenario, with the bull ceiling and the bear floor computed against the same attach framework so they are visibly in the same room. Then the named-competitor map, where AMD’s Strix Halo is the direct coherent-memory architecture on the desk and Qualcomm’s Snapdragon X is both the Windows-on-Arm precedent and the cleanest bear risk. The four-socket comparison table including the Apple bandwidth number that complicates the bull case. The phone flank, conceded honestly, NVIDIA has no current phone SoC. The ranked bear case down to the single cleanest way I am wrong. And the two-camps endgame, hardened against a skeptic who names all four players. The sizing is the work.

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JEDEC Said 8. Rubin Demanded 11. All Three Vendors Struggled.

Here is the line in the spec sheet almost nobody is reading. JEDEC, the body that standardizes memory, rated HBM4 at 8 gigabits per pin. NVIDIA’s Rubin asked for 11. A 38% reach, and SK Hynix, Samsung, and Micron all strained to hit it. Read that next to the fact that short-reach SerDes links, the ones already shipping in UCIe and NVLink die-to-die today, run at 32 to 64 gigabits per pin. Four to eight times faster. On the same silicon, in the same datacenter, in the same year.

That gap is the whole argument. The semiconductor analyst Irrational Analysis made it in a piece called “HBM: High Bandwidth Mistake,” and it stopped me cold this afternoon. So I had to think about this and break down his claim, stated simply: the problem was never the DRAM. The DRAM is fine. The problem is how we bolted it on. What follows is my attempt to translate his engineering argument for the rest of us, and to connect it to a piece of physics I have already written about from the other side of the stack.

The Chip Is a Kitchen. Memory Is the Pantry.

Think of the chip as a kitchen full of cooks, and memory as the pantry of ingredients. The cooks are fast. The question is always the same: how fast can ingredients reach them.

Today, with HBM, the only way to get ingredients fast enough is to bolt the pantry directly onto the kitchen wall, stacked floor to ceiling. It works. But the shelves are crammed together with thick support beams running through them. Those beams are the TSVs and micro-bumps, the through-silicon vias and the tiny solder contacts that stitch the stacked memory dies together. Each one adds a little electrical drag, what an engineer calls parasitic capacitance, and that drag is what caps how fast each pin can run. The beams also eat shelf space and make the pantry door narrow. So no matter how fast the cooks are, ingredients come through at a trickle.

And the pantry is stuck. You cannot move it. You cannot share it with the kitchen next door. All that stacked mass traps heat right next to the stove, so the cooks have to slow down to keep from cooking themselves. That is HBM in one image: a powerful pantry strangled by its own doorway.

The reframe is that simple. Memory bandwidth has been treated as a memory problem. It is really a shoreline problem: the doorway writ large. How much usable edge does the chip have, and how efficiently can data cross it? The DRAM was never the bottleneck. The doorway was.

His Fix: Rip the Pantry Off the Wall, Pipe It In From Down the Hall

So stop bolting the pantry to the wall. Put it down the hall, and connect it with a fiber-optic conveyor belt instead of a doorway.

The belt moves ingredients at near light speed with almost no delay. The door on the kitchen side is now tiny and efficient, a clock-forwarded SerDes feeding a simple receiver, which frees up wall space for more cooks. The pantry can be cheap, ordinary shelving, commodity LPDDR instead of expensive custom-stacked HBM. Any kitchen can draw from the same pantry. You can make it as big as you want. And with the heat moved down the hall, the stove can finally run hotter.

He is honest about the catch, and so am I. Building the conveyor belt is hard. Getting the data onto the fiber cleanly is, in his words, pain and suffering, and it is a few years out. Until then the smart move is a better-organized wall pantry, which is the commodity-LPDDR approach he likes from a startup called Positron.

I Already Wrote the Other Half of This Story

Here is the connection only this newsletter can make. The “clock-forwarded SerDes” at the heart of his fix is not a new idea to BEP readers. It is the exact same primitive I traced from NVIDIA’s ISSCC paper earlier this year.

As I wrote in The Fourth Piece: Why Groq Changes the GTC Thesis: “Optical clock forwarding lets NVIDIA connect multiple separate chips so they behave as one coherent processor. Same clock, same timing, every cycle.” In that piece, I read clock forwarding as the way NVIDIA makes separate dies act as one machine at rack scale, the physical layer that lets a dataflow inference engine stay synchronized. Same enabling technology. Opposite end of the stack. I covered it for unifying compute. Irrational Analysis applies it to disaggregating memory.

These are not competing theses. They are two consequences of the same physics. A forwarded clock over an optical link is so precise it can make two chips share one heartbeat, and that single capability eats the interconnect at both ends. On the compute side, it stitches dies into one coherent processor. On the memory side, it lets the pantry move down the hall. The piece of silicon doing the real work in both stories is the link, not the chip and not the DRAM.

The Bear Case: “Almost No Delay” Is Doing Heavy Lifting

I want to be honest about where the metaphor stretches, because two words in his pitch carry a lot of weight: “almost no delay.”

Light in fiber travels at roughly 5 nanoseconds per meter. A pantry 30 meters down the hall is a 60-meter round trip, so call it 300 nanoseconds of pure flight time before you touch anything. HBM bolted to the wall answers in roughly 100 nanoseconds. So the belt is wonderful for pooling capacity and bandwidth, the bulk ingredients you can fetch a little ahead of time. It is not a drop-in replacement for the latency-sensitive hot path, the ingredients the cook needs in the next half-second.

That distinction softens his most aggressive claim, his projection that HBM volume drops 90%. The honest version is that the optical pool becomes a memory tier, a big cheap warehouse behind a smaller fast wall pantry, not a full HBM replacement. The physics on the shoreline is settled. The demand-destruction timing is the speculative part. Hybrid bonding, the next-generation way of stacking dies without the bulky micro-bumps, may let HBM widen its own doorway and reclaim some of the shoreline it is losing.

Here is the cleanest way the whole reframe could be right and still not pay. If the co-packaged optical receiver never gets cheap and reliable enough to beat HBM-plus-hybrid-bonding inside an investable window, the shoreline argument is true and commercially irrelevant for a decade. So watch the receiver, not the slogan. The day a co-packaged optical link ships at an HBM-competitive cost per bit is the day the pantry actually moves down the hall.

And the largest caveat sits above all of it: NVIDIA. The company leads the entire stack, sets the roadmap the memory vendors chase, and has a long habit of engineering its way out of its own constraints rather than being disrupted by them. Apple did the same thing with the iPhone supply chain, turning the hardest manufacturing problem in consumer electronics into a moat nobody else could cross. Whichever way the shoreline resolves, NVIDIA is positioned to own it. Widen HBM’s doorway with hybrid bonding, or pull the optical link in-house and make the disaggregated pantry its own. Betting on this kind of disruption usually means betting against the incumbent, and the incumbent here writes the spec. That is the discipline in the call: the physics points one way, but the company best placed to capture it is the same one that built the wall pantry. Until that resolves, the fight is only over how fast HBM fades.

So What?

Stop thinking about memory bandwidth as a memory problem. Start thinking about it as a real-estate problem at the edge of the chip. That is the reframe to carry out of this piece, and it reorganizes the whole stack once you see it. The expensive, supply-constrained, heat-trapped thing we have been treating as the prize, the HBM stack, turns out to be a workaround for a doorway that was always too narrow. The real prize is the doorway itself, the link that crosses the shoreline. That is the layer the market keeps pricing as a cost when it is actually the control point.

I am not calling the end of HBM. The fight is only over how fast it fades.

Watch the shoreline, and watch the link that crosses it.

Credit

This is a free, standalone read, and there is no paywalled second half. Full credit to for the original engineering argument in “HBM: High Bandwidth Mistake.” I am translating it and adding the bear case, not improving on his physics. I would rather hand you the caveat straight than sell you the clean version.

Related BEP Research

• The Fourth Piece: Why Groq Changes the GTC Thesis

• The Memory Wall: Why Groq and Jamba Had to Find Each Other

• The DRAM Squeeze

• The Memory Wars

About the Author

Ben Pouladian is a Los Angeles-based tech investor and entrepreneur focused on AI infrastructure, semiconductors, and the power systems enabling the next generation of compute. He holds an electrical engineering degree from UC San Diego, where he worked in Professor Fainman’s ultrafast nanoscale optics lab on silicon photonics and micro-ring resonators, and interned at Cymer, the company that manufactures the EUV light sources for ASML’s lithography systems. Long-term NVIDIA investor since 2016.

Follow on X: @benitoz | More at bepresearch.com

Disclosure: The author holds positions in NVDA, BE, LITE, CRDO, TSEM, LSCC, ORCL 2027 Calls, and ALAB. This is not investment advice.

Marvell reported a record quarter, and the number that matters is not the $2.418 billion in revenue or the $0.80 of EPS. It is the FY28 guide, raised by $1.5 billion to roughly $16.5 billion, with data center growth accelerating rather than fading. On the call, CEO Matt Murphy named the reason without flinching: “Our customers continue to signal robust demand, not only for this year, but for the next several years.” That is not a company beating a number. It is a company telling you the demand curve is steepening.

Read that guide carefully. Most beat-and-raise prints nudge the out-year up by a rounding error. Marvell raised FY28 by $1.5 billion in a single quarter, and the data center growth rate steps up across three years, not down: 46% in FY26, 50% in FY27, 55% in FY28. A company digesting a demand pull-forward guides the out-years lower. A company watching the demand curve steepen guides them higher. Marvell just did the second thing.

The headline metrics are the floor, not the signal. Record revenue of $2.418 billion, up 28% year over year and 9% sequentially. Data center at $1.83 billion, 76% of the total and up 27% year over year. FY27 guided to roughly $11.5 billion, a 40% growth year. Q3 crosses $3 billion a quarter, a milestone management had previously framed as a Q4 event. The number underneath all of it: interconnect revenue raised to greater than 70% year-over-year growth, up from a prior framing of 50%, with 1.6T ramping, 400G-per-lane next, and the TIA and driver business already at a $1 billion run-rate.

This is a demand piece, not a Marvell piece. Marvell is the instrument panel: it sells optical DSPs, SerDes, AECs, coherent DCI, switching, and custom silicon into all five US hyperscalers, so when it raises the out-year by $1.5 billion and steepens the growth rate, it is not making a claim about its own share. It is reading the temperature of the entire system.

One Dot in a Larger Signal Stack

Marvell has functioned as a demand gauge in this coverage since March. In The Quiet Architect, the argument was that the value of watching Marvell is not whether you own it. It is that Marvell’s breadth across every connectivity layer makes its order book a system-level readout of where AI infrastructure spending is actually going.

And it does not stand alone. The same demand has surfaced across this coverage for six months: the physics case that copper had to give way to optics, Credo’s record prints, and NVIDIA’s $6 billion deployed across the optical layer. The cleanest statement of it was The Watt Asymmetry, where one megawatt per rack meant “optics have to move onto the rack itself.” Marvell’s print is the next leg of that same physics, not just optics onto the rack but optics between buildings, and the first system-level revenue confirmation of it. Marvell is the eighth dot, and it points exactly where the other seven do.

For paid subscribers: the content-expansion map, the public read-through basket, the NVIDIA DSP risk, and the prepayment tell that says supply, not demand, is still the constraint.

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“Olympus Cores Delivering The Best Performance Ever Seen On ARM.”

That was the Phoronix headline. It is accurate. It is also the least important sentence on the page.

Read what the benchmark actually settles, and what it does not. Lot’s of technical specs, sorry in advance: Phoronix measured NVIDIA’s new Vera CPU at 1.63x its own Grace predecessor on the geometric mean, 1.55x Intel’s 128-core Xeon 6980P, and roughly 10% ahead of AMD’s EPYC 9575F. The silicon underneath: 88 custom Armv9.2 Olympus cores, 176 threads via spatial multi-threading, FP8 support, 2MB of L2 per core and a 164MB unified L3 (double the L2 of Grace and a far larger L3), LPDDR5X delivering up to 1.2TB/s of bandwidth, PCIe Gen 6 and CXL 3.1, in a 450W socket that lands near 500W with memory, broadly comparable to the x86 parts it is built to displace.

Those numbers are real. They are not the point.

The point is which socket just changed hands. For years NVIDIA has been moving the unit of competition from the chip to the rack: it builds the GPU, the networking through NVLink and Spectrum, and the coherent CPU-GPU link through NVLink-C2C. One socket was still a merchant part, bought from Intel or AMD: the head-node CPU. Vera is that socket. With Vera, the last major merchant socket moves in-house.

The benchmark is the distraction. The ownership map is the story.

The CPU Stopped Being a Supporting Actor

The head-node CPU only became worth winning because agentic AI made it worth winning.

The AI narrative was GPUs: more FLOPS, more HBM, more NVLink. The CPU booted the server, coordinated the system, and stayed out of the narrative. Agentic workloads broke that. The orchestration between GPU calls now lands on the CPU, and at GTC Jensen put a number on it: 12,000 GPUs require 400,000 CPU cores for agentic AI and reinforcement learning, a 33-to-1 core ratio.

The clearest statement of why the socket matters came from the person whose company licenses the cores underneath it. In The Agentic CPU, Arm’s Mohamed Awad told me after the keynote: “The GPUs are gonna generate the tokens, the CPUs are gonna figure out what to do with them. As more and more tokens get generated, you need more and more CPUs to handle it.” That orchestration socket used to be rented from x86. Vera ends the lease.

Vera Closes the Loop

The reframe paid readers carry from here is The Last x86 Island: the head-node CPU was the final major merchant socket in NVIDIA’s AI rack, and Vera takes it in-house.

This is the layer NVIDIA spent a decade assembling everywhere else. In NVIDIA’s Inference Stack Depth Strategy: “They sell chips; NVIDIA sells stack depth.” That line was written about the GPU. It now applies one socket lower. A merchant vendor sells a CPU. NVIDIA sells a CPU designed knowing the exact GPU it feeds, the exact fabric it talks across, and the exact runtime it schedules for. Vera exists to feed the Rubin GPU over NVLink-C2C. That is not a spec-sheet comparison. That is a different product category.

The stack-depth tell is in the boring infrastructure. NVIDIA upstreamed Olympus compiler support into GCC and LLVM Clang more than a year before the chip ships. Kernel support is already upstream. Vera boots on stock ARM64 distributions like Ubuntu and Fedora through ACPI, with no Device Tree headaches. That is what owning the stack looks like two layers below the headline.

The table is the whole argument in one frame. Four CPUs, one power envelope, one benchmark sweep. Vera leads each measured geomean. But the column that matters is the last one: NVIDIA Vera and Grace are in-house silicon; AMD EPYC and Intel Xeon are the merchant parts being displaced.

The benchmark column will be stale in a quarter. The ownership column will not.

The benchmark tells you Vera is fast. The ownership map tells you why AMD and Intel should care. Below the divider: why winning the socket beats buying it, the perf-per-watt math that turns a CPU spec into a cost-per-token line, the three bears ranked by what actually changes the thesis (including the one chip that could retake the raw lead this year), and the read across NVDA, AMD, INTC, and ARM.

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Scarcity Is the Asset.

“Weekends are for philosophy.”

Ram Ahluwalia had the right line for the moment.

The SpaceX discourse this week is mostly about the multiple.

The $2 trillion implied valuation. The hundreds-of-x sales multiple. The obvious-bubble framing.

The complaint is reasonable. It is also pointed at the wrong artifact.

Friends and subscribers have been asking me the same question all week: do I buy the SpaceX IPO, or is this the top? I know several early investors who are quietly relieved to finally get liquidity after a decade-plus hold. I am on the fence personally. What follows is the framework I am using to sort it.

The Tell

SpaceX filed hundreds of pages.

It talked about Mars.

It talked about AI.

It talked about a $28.5 trillion TAM.

What it did not talk about was the thing that may matter most: power.

That is the tell.

Ed Ludlow surfaced it yesterday on X, sourced from Bloomberg’s Kara Carlson and Mark Chediak. SpaceX is building a 10 gigawatt solar manufacturing facility in Bastrop, Texas. 1.1 million square feet across two floors at 5 GW per floor. Bloomberg frames the purpose plainly: power for the next generation of Starlink satellites, and power for the orbital data centers Elon Musk has been describing publicly for two years. A billion-plus-dollar industrial program. The S-1 names Bastrop and says SpaceX will more than double the facility in 2026 to add Starlink gateway antennas, solar cells, and AI compute satellites. The 10 GW scale is not in the filing.

The disclosure layer is selling Mars and AI. The construction layer is buying power.

What the Multiple Bears Are Missing

The obvious critique is that SPCX does not screen on sales. That is true and not interesting.

The better question is why the market is willing to suspend the screen.

The answer is control. SpaceX is not being valued as Starlink plus rockets. It is being valued as a vertically integrated stack: launch, orbit, broadband distribution, AI compute, power manufacturing, and eventually orbital data center optionality.

The multiple looks insane if the asset is Starlink revenue. It looks less insane if the asset is the only credible path from ground power to orbital compute.

That is the read.

Scarcity Is the Asset

The combined post-money on OpenAI, Anthropic, and SpaceX is about $4 trillion. The combined annualized revenue is about $80 billion. The implied multiple is roughly 50x sales.

That number is not a DCF output. It is the price of control. A scarce asset is not priced like a factory. It is priced like a unique control point. One OpenAI. One Anthropic. One SpaceX.

Each of the three privates controls something the market has decided cannot be easily replicated:

• OpenAI: frontier capability and consumer distribution.

• Anthropic: enterprise trust and model quality at the agentic edge.

• SpaceX: orbital coverage, launch capacity, and now power.

Run the three numbers.

OpenAI: $852B post-money on a $24B run rate, ~35x sales. The $122B raise closed March 31, 2026. Q1 2026 revenue at $5.7B, annualizing to $24B. Mix is 45% ChatGPT consumer, 35% enterprise API, 20% platform and Microsoft licensing. Enterprise revenue is on track to parity with consumer by year-end.

Anthropic: $900B-plus pre-money in talks on a $43B run rate, ~21x sales. The Series G closed at $380B post on February 12. A new round is in discussion as of late April at $40 to $50B raised on $900B-plus pre-money, per TechCrunch. The April 2026 annualized run rate is $43B, up from $9B at the end of 2025. That is 4.8x in four months. The 1,000-plus $1M-plus customers doubled in under two months.

SpaceX: $2 trillion implied on roughly $18B Starlink run rate, more than 100x. Starlink is more than two thirds of revenue and printed $1.2B of profit last quarter. At the implied $2T equity value, Starlink alone underwrites a multiple north of 100x. And the 10 GW Bastrop scale is not in the S-1.

The honest read on SpaceX: I am on the fence about when orbital data centers actually scale. Maybe 2028. Maybe 2032. Maybe never at the scale being implied. But the timing is not what is repricing the equity. The AI narrative is. SpaceX is going public as the only private company with a credible story across launch, satellites, AI compute, and power. The IPO pop is being underwritten by that narrative, not by the discounted cash flow of orbital data centers.

Anthropic is growing fastest and pricing cheapest. SpaceX is growing slowest on the revenue line and pricing richest. In any normal sales-multiple framework, the faster-growing name carries the higher multiple. None of these three behave that way.

The multiple is not tracking growth. It is tracking what each company controls that nobody else can easily replicate.

Below the divider: the rack-power roadmap, the public-market overflow map, the six-name action framework across power, optics, foundry, and connectivity, and the six S-1 reads that decide whether SPCX is a scarcity asset or a public-market comp trap.

BE, LITE, COHR, TSEM, CRDO, ALAB, plus SPCX itself.

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Jensen’s closing remark on the FQ1 FY27 call inverted every “are we peaking” preview note in one paragraph: “Demand has gone parabolic. The reason is simple. Agentic AI has arrived. AI can now do productive and valuable work. Tokens are now profitable, so model makers are in a race to produce more. In the AI era, compute capacity is revenue, and profits. NVIDIA is the platform of this era.”

That is the cold open the consensus framework did not have language for. The Street walked into the print asking whether NVIDIA’s growth rate could survive a step-down in hyperscaler capex composition. Jensen answered with the inverse mechanic: hyperscaler capex is rising into a workload curve where every deployed token is profitable, and compute capacity itself is the revenue. The framework Monday night’s piece used to anticipate this print was simpler. Five lines. Each one a mechanical question. The print either marks them or refines them.

This is the post. Total revenue $82B, up 85% year over year and 20% sequentially. Data center $75B, up 92% year over year. Jul Q guide $91B plus or minus 2%. Gross margin 74.9% GAAP, 75% non-GAAP, flat sequentially. Free cash flow $49B against $35B the prior quarter. Dividend stepped from a penny to a quarter (Jensen corrected Colette’s $0.20 read live on the call to $0.25). An $80B new buyback authorization on top of $39B remaining. And one new TAM disclosure that re-rates the multi-year shape of the business: Vera CPU, $200B TAM, $20B standalone revenue this year, and explicitly not in the $1 trillion Blackwell-plus-Rubin number Jensen reaffirmed at GTC.

The Map, Posted Monday Night

From The Cheap Chip Trap Jensen Just Confirmed At Dell World: “Five lines on Wednesday’s print decide whether the thesis ratifies or refines. Data Center revenue: a clean beat above Street says hyperscaler procurement is already pricing the cost-per-token math. Jul Q guide: a number meaningfully above Street with gross margin holding says Rubin pricing power is intact. Cumulative Blackwell-plus-Rubin: any incremental update on the $1 trillion GTC disclosure is the demand-side ratification. NVLink Fusion: how aggressively NVIDIA monetizes the fabric advantage. Gross margin into Rubin first launches: holding through 2H26 says hyperscalers are paying NVIDIA’s gross margin to capture the perf-per-watt advantage.”

Five lines. Posted Monday night. Each one a mechanical question with a binary answer the print either marks or does not. Below the divider, each line gets walked against what the call delivered, with the consequence laid out for the ticker map. The pre-print thesis was that the Cheap Chip Trap squeezes ASIC procurement at megawatt density. The print ratified the demand-side capture on four of five lines, with the fifth refined upward by a TAM disclosure no preview note priced in.

Why The Lines Were The Lines

The five lines were not arbitrary picks. Each one is the mechanical proof point for a different layer of the thesis stack the BEP archive has been compounding for fifteen months. Run the mapping.

Data Center revenue is the demand-side proof for the Cheap Chip Trap. A clean beat above consensus says hyperscaler procurement has already run the perf-per-watt math at megawatt density and accepted that NVIDIA’s gross margin is cheaper than the operational drag of a custom ASIC. The print: $75B, up 92% year over year, 21% sequentially. Data center computing $60B, networking $15B (nearly tripled YoY on XDR InfiniBand and a Spectrum-X book “larger than all Ethernet network peers combined” per Colette). The procurement spreadsheet bought perf-per-watt. The line marked.

Jul Q guide is the supply-side proof. NVIDIA does not ship into demand it cannot fulfill. The guide came in at $91B plus or minus 2%, with gross margin held at 74.9% / 75%. Supply commitments stepped to $145B (inventory purchase commitments plus prepaids). The guide is the binding-constraint update in dollars: CoWoS, HBM4, and substrate capacity have moved up the curve enough to ship a $91B quarter while holding gross margin into a Rubin-overlap window.

Cumulative Blackwell-plus-Rubin is the order-book mark. Jensen reaffirmed the $1T figure from 2025 through calendar 2027. The refinement worth pricing in: in Q&A with Goldman’s Jim Schneider, Jensen confirmed that Vera standalone CPU revenue (the new $200B TAM) is not in the trillion-dollar number, and named it as the second-largest source of upside above the trillion line. The order book gets larger by inspection.

NVLink Fusion is the optical and interconnect monetization story. The fabric advantage is the part of the moat the chip-level perf-per-watt chart understates. From The Token Explosion: “NVIDIA Dynamo 1.0, announced at GTC and now in production, is the distributed operating system for AI factories. If the Vera Rubin platform is the factory floor, Dynamo is the manufacturing execution system — routing requests, managing memory, orchestrating heterogeneous hardware, and optimizing for latency or throughput depending on the workload.” NVLink Fusion is the physical fabric Dynamo orchestrates.

The call did not put a hard NVLink Fusion licensing number on it this quarter, but Colette named Spectrum-X as larger than all Ethernet network peers combined, and InfiniBand growing more than 4x year over year on XDR deployments. The implicit mark is in the networking line: $15B for the quarter, nearly tripled year over year, growing faster than data center computing.

Gross margin into Rubin first launches is the pricing-power proof. A new product launch typically compresses margin in the first quarter or two of volume ramp. Colette guided 74.9% / 75% for Jul Q and reiterated mid-seventies for the full year, with Blackwell Ultra delivering “a 2.7x increase in throughput and a 60% reduction in the cost per token on GV300 compared to just 6 months ago.” Hyperscalers are paying NVIDIA’s full sticker for perf-per-watt while NVIDIA is internally lowering cost-per-token. The margin holds. The token economy improves. Both sides of the trade clear.

Five questions. One print. Four clean ratifications and one refinement upward via the Vera CPU TAM disclosure.

Below the paywall: the line-by-line scorecard with the print numbers filled in, the Vivek Arya / Vera CPU exchange where Jensen disclosed the Token Dollar mint mechanic live on the call, the cost-per-token waterfall rebuilt against the GV300 2.7x throughput and 60% cost reduction, the four-name watchlist read-through (LITE, CRDO, TSEM, MU), and the four named bear cases the print sharpened rather than retired.

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"NVDA's FLOPs per Chip Divided by Watt Consumption is anywhere from 2x-8x ahead of current-gen, custom ASICs."

That is the headline of slide 17 from Morgan Stanley Research's NVIDIA preview note. The chart shows Vera Rubin on NVFP4 at the top of the page at 19.5 TFLOPs per watt. Amazon's Trainium 3 sits at the bottom at 2.5. Google's TPUv7 lands closer to the ASIC line than to Vera Rubin. The note frames it cleanly: raw silicon remains key in increasing performance per watt.

The Street is modeling the wrong line. The Goldman, Wells Fargo, and UBS previews this week all walked Data Center revenue, the $1 trillion cumulative Blackwell-plus-Rubin disclosure Jensen made at GTC, and gross margin into Rubin first launches. None of them led with the metric that decides which hyperscaler stack wins through 2028. That metric is cost per token at a megawatt-class rack, and on that metric NVFP4 is not an incremental improvement. It is a category-redefining move that inverts the entire "custom silicon is cheaper" procurement story hyperscaler CFOs have been told for three years.

This is the post. The reframe paid subscribers carry from here is The Cheap Chip Trap: a custom ASIC procured for its dollar-per-chip discount commits the buyer to a megawatt-per-token disadvantage for the operational life of the asset. The trap is not the chip price. It is the gigawatt that has to feed the chip for the next five years.

Reading The Chart

The Morgan Stanley chart is doing something specific most readers will miss. The Vera Rubin bar at 19.5 TFLOPs per watt is measured at NVFP4. Every other accelerator on the chart, including both custom ASIC bars, is measured at FP8. That is not a unit comparison. That is a workload comparison. The next generation of frontier inference is moving from FP8 to FP4. NVIDIA designed silicon for that workload. The current ASIC roadmaps did not.

Even on an apples-to-apples FP8 basis, Vera Rubin produces multiples more tokens per watt than Trainium 3, on the precision Trainium was designed for. Shift the workload to FP4 and the gap widens substantially further. TPUv7 fares better but still trails Vera Rubin at every precision. The Morgan Stanley footnote concedes the point: Trainium 4 and TPUv8 will also support FP4, both shipping in 2027 at earliest. The Vera Rubin gap is being marked today.

From The Watt Asymmetry: "The 50x perf-per-watt improvement from Hopper to Blackwell is the single cleanest expression of the Watt Asymmetry response. The full vertically integrated bundle (GPU plus CUDA plus NVLink Fusion plus Dynamo plus TensorRT-LLM plus DSX plus Omniverse plus Emerald AI) is what lets American data halls produce more tokens per watt than anyone else." The Morgan Stanley chart is the silicon-only slice of that answer. Add HBM4e bandwidth, NVLink Fusion at NVL576, Spectrum-X scale-out, and Dynamo serving on top, and the system-level cost-per-token gap is wider than the chip-level chart implies.

Why ASICs Chose Up Front, And Pay Forever

The custom silicon pitch to a hyperscaler CFO is simple. The wafer cost is yours, not NVIDIA's gross margin. The design is tuned to one workload, not a fungible GPU. Per chip on a procurement spreadsheet, the ASIC wins. The procurement spreadsheet is the top of the iceberg. The line that decides cost structure sits below the waterline, denominated in megawatts.

The Chip Is Dead, Long Live The Factory put it this way: "A custom ASIC that beats NVIDIA on cost-per-GPU-hour but delivers a fraction of the tokens per megawatt is not a bargain. It is a factory that cost you less to build and costs you far more to run." The Morgan Stanley chart is the empirical mark on that claim. A Trainium 3 rack commits the same megawatt of grid, cooling, and 800V DC rectification as a Vera Rubin rack. The wafer was cheaper. The megawatt was the same. The tokens produced were a fraction.

Layer the second variable hyperscalers face: the US grid will not interconnect new megawatt load on commercial timelines. ERCOT has paused new interconnect studies. PJM's queue runs into the 2030s. The megawatt you have today is the megawatt you have for the duration of your AI factory. Every token you do not produce from that megawatt is a token your competitor produces on Vera Rubin. That is not a procurement decision. That is a strategic capacity decision the spreadsheet has been pricing wrong.

I made the same point last week in Inference Never Sleeps: "Continuous inference at production scale is a sustained, high-utilization load, not a bursty one. Robot fleets, voice agents, video collaboration. Every deployed humanoid is a 24/7 inference duty cycle. Inference Never Sleeps, and the watt bill compounds." The procurement spreadsheet sized today's bursty chatbot workload. The deployment fleet through 2028 runs 24/7, and the perf-per-watt gap compounds against the duty cycle.

Jensen confirmed the duty cycle on stage at Dell World this afternoon with Michael Dell: "We're going to have billions of AI agents, and they're going to be working 24/7." The principal said it out loud forty-eight hours before the print.

Below the paywall: NVFP4 as a system rather than a format, the cost-per-token math at one megawatt per rack through 2028, the four bear cases ranked by what I am watching into Wednesday's print, the ticker map across NVDA, AVGO, MRVL, GOOGL, AMZN, and TSEM, and the five lines on the print that decide whether the thesis ratifies or refines.

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Three Labs, One Architecture

AI is moving from turn-based, harness-bolted, reactive architectures to continuous, native, predictive ones grounded in time. The model no longer waits for the user to finish typing before it starts thinking. Robots no longer pick the next action one observation at a time. Voice agents no longer take turns. The whole system runs on, all the time, perceiving and acting in the same continuous loop. Inference Never Sleeps.

That is the architectural bet. Three frontier AI labs just shipped the same version of it in five weeks, from three different directions.

Horace He, an engineer at Thinking Machines and formerly a core contributor to PyTorch, posted the cleanest framing of what Mira Murati’s team just shipped: “Model intelligence has exploded, causing the bottleneck to be human↔AI bandwidth.” Same memory-wall logic BEP has been mapping since The Memory Wars, applied to the human side of the loop. Disclosed by an engineering insider, in public, on the day the model shipped.

NVIDIA’s DreamZero made the recipe concrete in February. As I wrote in The World Model Reckoning: “DreamZero jointly predicts video and actions in the same diffusion forward pass... the future in pixels, and the robot executes based on that dream.” That was the GPT-2 moment for Physical AI. Physical Intelligence’s Pi 0.7, released April 2026, is described in the paper as a “steerable generalist robotic foundation model” conditioned on multimodal prompts. Thinking Machines, Mira Murati’s lab, shipped TML-Interaction-Small on May 11, 2026 with a different vocabulary but the same insight: “For interactivity to scale with intelligence, it must be part of the model itself.”

Three labs. Three problem domains. One architectural recipe. That convergence is the thesis.

Turn-Based Is the Harness. Continuous Is the Architecture.

The first instinct on these three releases is to call them faster reactive systems. That framing is correct but incomplete. The deeper shift is rejecting the turn-based primitive every frontier model has been built on for the last decade.

Thinking Machines (TM) names it directly: “Today’s models experience reality in a single thread. Until the user finishes typing or speaking, the model waits with no perception of what the user is doing or how the user is doing it. Until the model finishes generating, its perception freezes.” Their solution is a 200ms micro-turn architecture that streams audio, video, and text simultaneously. The model perceives and responds in the same continuous loop.

Horace He extended the framing mechanically the same week: “Hybrid systems like DRAM kv-cache + SRAM weights (interaction models + autonomous agents) that can get the best of both worlds.” The hybrid he names is the exact split TML-Interaction-Small validates in production. A continuous-perception interaction layer running 200ms micro-turns. An asynchronous background reasoning layer that keeps the deeper thinking in a slower loop.

Disclosed by an engineering insider. In public. On the day the model shipped.

The architectural recipe is no longer disputed inside the labs.

This is the same primitive as DreamZero. A VLA (vision-language-action model, the standard reactive architecture) picks the next action from the current observation, one turn at a time. A WAM (world action model, predictive by design) rolls counterfactual trajectories forward across time, scoring them continuously as new sensor data arrives. Pi 0.7 does the same thing from the policy side, conditioning on subgoal images and strategy metadata to “steer the model precisely to perform many tasks with different strategies.”

TM cites the precedent explicitly: “Some domains take such interactivity as a given. The physical world demands that robotics and autonomous vehicles operate in real time.”

Tesla validated the pattern in cars two years before any of the labs caught up.

Every Tesla running v12 or later is a continuous world-model rollout. End-to-end neural net inference at highway speed, on a vehicle the customer already paid for. The Continuity Convergence is the automotive architecture pattern applied to everything else. Mira Murati’s team built the language-domain version of what NVIDIA and Physical Intelligence built for robotics. The Bitter Lesson applied to interaction. Hand-crafted harnesses lose to learned end-to-end systems.

Turn-based is the harness. Continuous is the architecture. Inference Never Sleeps.

Same abstraction, three entry points. WAMs provide predictive world dynamics. Steerable policies provide controllable behavioral interfaces. Interaction models provide continuous bidirectional perception. The shared primitive is continuous inference grounded in time, not call-and-response. The recipe is the same one NVIDIA has been co-designing the rack-scale platform for since GTC 2026: GPU plus LPU plus Vera CPU plus DPU plus NVLink plus Dynamo. The hardware was ready before the model paradigm asked for it.

The thesis slogan: Inference Never Sleeps. The named framework: The Continuity Convergence. Below the divider: three worked deployment scenarios (humanoid fleet, continuous voice agent, screen-watching coding agent), the unit-corrected token math, the memory wall that just got three new axes, the six-layer investment map with the centerpiece insight nobody is sizing correctly, and the three named risks that could break the timeline.

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“Google is obviously doing very, very well in the market.” And: “Google is driving a lot of demand on our business.”

That is Lumentum CEO Michael Hurlston this afternoon, answering a sell-side question that opened with the news of the day: The Information had just reported that Anthropic committed to spend $200 billion with Google Cloud over five years, beginning in 2026. Anthropic alone is now responsible for more than 40 percent of Google’s disclosed revenue backlog. Anthropic plus OpenAI together account for more than half of the $2 trillion in contractual cloud-provider backlogs sitting on the tape today. The deal brings well over a gigawatt of compute capacity online in 2026.

As I wrote in “The Token Dollar”: “Borrow dollars, buy GPUs, mint tokens, sell tokens for dollars, service the carry.” The Anthropic-Google announcement is the principal. The four earnings prints reported in the same trading window are the carry getting marked into the income statement. The thesis I forecast Friday in “The Watt Asymmetry” is now a tape.

Eaton: The Industrial Layer Just Confirmed the Thesis

Q1 revenue $7.5 billion, up 17 percent with organic growth of 10 percent (three points above the high end of February guidance). Adjusted EPS $2.81 was a Q1 record. FY26 organic growth guidance raised 200 basis points at the midpoint to 9-11 percent.

The number that matters is the order book. Electrical Americas posted record sales of $3.6 billion at 25.6 percent operating margin, with twelve-month rolling orders up 42 percent organically. Total backlog is up 44 percent year over year. Electrical Global backlog is up 73 percent. Eaton also closed eleven billion dollars of strategic acquisitions including Boyd Thermal, the cooling layer that sits next to its own power layer inside the same rack. As I wrote Friday: “The Watt Asymmetry is pricing through the industrial layer in real time.” The 42 percent organic order growth is what that looks like in a $14B segment. This is not a cycle, it is a single-trade demand pull.

Below the paywall: how Lumentum’s billion-dollar Q4 guide names Google as the demand driver, why Astera’s Scorpio X-Series is a content-expansion print masquerading as a unit print, what Wolfspeed’s “purpose-built for AI racked power” disclosure means for the asset story, ServiceNow’s FAD as the Layer 7 mark, the bear case, and the watch list.

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This piece is for paid subscribers only. The idea is in the body. The reason this is paid-only is structural, not promotional: the asymmetric setup that makes this position worth taking does not survive a public reveal. Float is thin. Short interest is heavy. The path-of-trade depends on subscribers acting on the framework before the next wave of capital prices it through. I am taking the position myself.

The Watt Asymmetry parent piece named six layers, three names, and one binding constraint: the megawatt rack on a US grid that will not interconnect new load for eight years. Nvidia, Eaton, Bloom carry the framework across silicon, power distribution, and behind-the-meter generation. Three tickers a portfolio manager can size today on the published thesis alone.

I deliberately did not name the fourth.

As I wrote on May 1 in The Watt Asymmetry: “The Watt Asymmetry is pricing through the industrial layer in real time.” That sentence covered the cabinet, the busbar, the fuel cell. It deliberately stopped one node above the silicon that does the conversion inside the cabinet. The reason is that the fourth name is a bottleneck trade, and a bottleneck trade is a different posture than a framework allocation. It is asset-driven, not earnings-driven. It sits inside a balance-sheet thesis the sell-side cannot model from the income statement. It carries an asymmetric setup the cap table makes possible. And it deserves to be priced in by my paid subscribers before it prices in publicly.

This is that name.

The Layer the Watt Asymmetry Did Not Name

The parent piece organized the AI build-out into six layers: silicon, memory, advanced packaging, optical interconnect, power distribution, and behind-the-meter generation. Layer 5 was Eaton: medium-voltage switchgear, busbars, the 800V DC power chain, grid-interconnect engineering. Layer 6 was Bloom: native 800V DC fuel cells, 90 to 120 day deployment, capacity bear thesis retired in a single Q1 print.

What sits between them is the silicon. Specifically, the 1200V silicon carbide MOSFET die that turns the 800V DC bus into the 54V, 12V, and sub-1V rails the GPU actually consumes. Eaton sells the cabinet. Bloom sells the watts. Neither makes the device class that does the conversion. At one megawatt per rack, every conversion stage has to clear that voltage with under 2 percent loss or the thermal envelope breaks.

Industry data on conversion losses puts SiC’s advantage at 25 to 40 percent versus silicon at this voltage class. Below 800V, silicon still works. At 800V and above, SiC is the part. The reference designs are public: Eaton, onsemi, Infineon, and ST have all published 800V DC architectures against the NVIDIA Kyber rack-scale spec, and every one of them puts 1200V SiC into the AC-DC rectification stage, the solid-state transformer, and the first DC-DC step-down. This is not a substitution story. It is a content-expansion story.

And the content-expansion story holds even where Bloom wins. Native 800V DC generation removes the AC-DC rectification stage at the facility level, but the rack still needs DC-DC step-downs from 800V to 54V to 12V to sub-1V. The high-voltage stages of that chain are SiC regardless of where the 800V comes from. Where the grid serves, the rectification chain is full SiC. Where Bloom serves, the rectification chain shrinks but the rack-level SiC content does not go to zero. Both paths increase silicon carbide consumption per kilowatt of AI compute. Both paths make the asset more valuable.

One US-domestic player owns the only fully-built 200mm silicon carbide device fab on US soil. It just emerged from bankruptcy. The market is pricing it against the income statement. The asset is the entire story, and the asset is mispriced. The public reframe is The Watt Tax. The trade structure is bottleneck. The asset itself has a name. That name is behind the paywall.

Below the paywall: the name, the trade, the court-anchored $2.6B nobody is modeling, the cold-open insider quote, the bottleneck thesis, the cap table that makes the asymmetry tradeable, how I am sizing, five charts.

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Subscriber Exclusive

I recorded a conversation last week with JP Buzzell, VP and Data Center Chief Architect at Eaton. The podcast drops for everyone in about a week. Paying subscribers are getting the investment call first.

“The United States is scarce on energy.”

That was Jensen Huang on the Dwarkesh Podcast two weeks ago, in a ninety-minute conversation that the market mostly read as a China export-controls debate. The more important framing sits three sentences later in the same exchange. Jensen laid out what he called the five-layer cake of AI, and at the bottom of the cake, below chips and models and applications, is energy. His argument: when you have an abundance of energy, it makes up for chips. When you have an abundance of chips, it makes up for energy. China has the first condition. America has the second. That structural asymmetry is the most important framing the market has been handed in months.

The Watt Asymmetry

The market read the Dwarkesh interview as a chip-export argument. The structural read is that Jensen just named the investable thesis of the next three years. China’s abundance of energy lets it run older chips in parallel. America’s scarcity of energy forces it to build the most efficient stack in the world. The investable question is not who wins the chip race. It is who builds the stack that makes scarce American watts go furthest.

JP is the primary source behind this piece. He operated commercial reactors in the US Navy for twelve years, taught nuclear operations for three, designed critical facilities at Meta and the first Zettascale data hall at Oracle, and recently co-led the release of the OCP DCF Power Distribution LVDC white paper: a 155-page document 200 companies signed onto as the first common-language framework for the power stack at AI scale. His frame on the physical layer and Jensen’s frame on the five-layer cake are the same argument seen from opposite ends of the telescope.

The Hyperscalers Just Confirmed the Budget

Forty-eight hours ago, the demand side of the Watt Asymmetry got marked. Microsoft, Meta, Alphabet, and Amazon all reported Q1 2026 on April 29 and all four either reaffirmed or raised their AI infrastructure capex commitments. Per Jefferies post-call consensus, the combined 2026 number is now $693 billion, up 13% in 48 hours from $613 billion pre-print. The 2027 consensus moved by the same percentage, from $723 billion to $821 billion. This is the largest two-year concentrated infrastructure cycle in technology history, and it just got bigger.

Alphabet raised 2026 capex to $180-190 billion, up from $175-185 billion, and CFO Anat Ashkenazi guided 2027 capex to “significantly increase” from there. Google Cloud revenue grew 63% to $20 billion. Microsoft guided full-year capex to roughly $190 billion with Q4 alone above $40 billion, and CFO Amy Hood said the company expects to remain capacity-constrained through all of 2026. Meta raised its 2026 capex range to $125-145 billion from $115-135 billion, citing higher component pricing (memory, primarily) and additional data center costs to support future-year capacity. Amazon projected 2026 capex of approximately $200 billion, with AWS revenue up 28% year over year, the fastest growth in fifteen quarters. The Watt Asymmetry is no longer a forecast. It is a budget. Every dollar in those numbers eventually becomes a watt that has to land at one megawatt density, in a refrigerator-sized space, in an American jurisdiction where the grid will not interconnect new load for eight years.

Downstream Design

JP’s central claim is a causal chain the investment community has been modeling backwards. Software drives network protocol. Network protocol drives rack density. Rack density drives cooling architecture. Cooling architecture drives the transition to direct current. The stack is downstream, not upstream. Most PMs model the AI build-out from the chip down. JP models it from the workload down.

The number that makes this concrete is rack power density. Hyperscale halls a few years ago ran 10 kilowatts per rack. Zettascale pushed that to over 100 kilowatts. Blackwell NVL72 is already at 120 kilowatts. Rubin brings 300 kilowatts. Feynman-generation reference designs target 600 kilowatts to one megawatt per rack. That is not a five-year ramp. That is a three-year ramp. One megawatt per rack is the same power as three hundred American homes, delivered into a space smaller than a refrigerator, over copper and optics that have to survive inside the same enclosure.

At that density, every architectural assumption in the hyperscale handbook breaks. You cannot deliver a megawatt at 48 volts, so the rack has to move to 800V DC. Run the arithmetic: at 48V, one megawatt per rack requires roughly 20,800 amps of current, the equivalent of the main breakers of 200 American homes running simultaneously through a single rack’s power path. NVIDIA’s own estimate is 200 kilograms of copper busbar per rack at that architecture, the weight of three adult men concentrated into the power spine of one cabinet. You cannot cool a megawatt with air, so liquid cooling becomes mandatory. You cannot run copper interconnects at the lengths and bandwidths required without bleeding watts to resistive loss, so optics have to move onto the rack itself. This is the physical expression of the Watt Asymmetry. If American power is scarce and American racks are running at a megawatt, the only path that works is extreme co-design across every layer simultaneously. China does not need to do this. As Jensen pointed out on Dwarkesh, if your watts are abundant, you can keep using older chips in parallel, and 7-nanometer chips are essentially Hopper anyway.

The Industrial Answer: DSX, Omniverse, Emerald AI

If the Watt Asymmetry is the problem, NVIDIA’s platform stack is the answer, and it runs three layers deep. At the physical layer sits the DSX Beam design, Eaton’s implementation of NVIDIA’s DSX blueprint, engineered for both current Blackwell racks and the coming Rubin and Feynman generations, and engineered for both legacy AC and the 800V DC architecture that becomes mandatory above 600 kilowatts per rack. Above DSX sits NVIDIA Omniverse, which lets an operator physically simulate the full facility, power and cooling and optical routing, before a single spade breaks ground. Above Omniverse sits Emerald AI, the orchestration layer JP described as good grid citizen behavior: finding stranded capacity on the grid, routing workloads in real time, and delivering fault ride-through that keeps a training run alive through waveform events.

The OCP Paper as Signal

Just before the Dwarkesh interview, JP co-led the release of the OCP DCF Power Distribution LVDC white paper. 155 pages. 200 companies aligned. The paper itself is not the catalyst. The signal is. Two hundred companies across silicon, cloud, and power OEMs coordinated on a common language for 800V DC because every one of them is about to spend real capex building against it. Version 1.1 focuses specifically on rack and power distribution, which is the layer where the transition actually lives. Coordinated standards arrive before coordinated capital, and the capital is coming.

Below the paywall: the named companies at every layer, the three names that carry the thesis, the EV supply chain that quietly built the 800V backbone before hyperscalers needed it, what Eaton's May 5 print has to show, the Bloom Q1 numbers Wall Street undercounted, and the short thesis that would force me to cover.

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The wires will lead with the numbers. Q1 product revenue up 208 percent year over year. Non-GAAP EPS at $0.44 against a $0.13 consensus, a 3.4x beat. GAAP net income flipped from a $23.8 million loss to $70.7 million. Adjusted EBITDA roughly 6x.

Then they will lead with the guide raise. Management moved every line: revenue, margin, operating income, EPS.

What the wires will not lead with, and what the sell-side notes Tuesday morning will likely undercount, is what K.R. disclosed in Q&A. Three operational data points that should reset the bull case, plus a TAM-expansion comment that nobody on the call seemed to fully register. The print is the catalyst. The Q&A is the thesis.

The Guide Caught Up

Two weeks ago, in “Oracle Just Signed the MSA Bloom Was Waiting For,” I closed with a watch list for tonight’s call. The first item: “does management raise full-year guidance, or hold and let the upside accumulate into the back half?”

Management raised. Not at the margin. Every line moved. From the call:

“The strength of the quarter and the commercial momentum we see across the board gives us conviction and confidence to raise guidance materially... You can see we are prioritizing growth and profitability in equal measure.“

Read that last line carefully. The standard sell-side bear pushback for a guide raise of this magnitude is “they bought it with margin.” K.R. and Simon pre-empted that on tape.

In February I modeled $1.40 in non-GAAP EPS for 2026 and roughly $3 to $4 in 2027. Tonight management put up a 2026 EPS range that lands above my prior number by 30 to 60 percent. They did not let upside accumulate into the back half. They pulled it forward.

This is not a beat-and-raise quarter in the ordinary sense. It is the quarter where the P&L caught up to a backlog the market had already been told about. The contracts were signed. The customers were named. The 800V DC alignment was published in writing by an Oracle EVP on April 13. What was missing was the management number that converted those facts into a forward earnings line analysts could put in a model.

Twenty-Five Years to Product-Market Fit

Bloom Energy was founded in 2001. K.R. Sridhar spent twenty-five years refining solid oxide fuel cell technology, driving manufacturing cost down, qualifying servers in commercial and industrial deployments, and waiting for a customer base whose demand profile matched what the product was actually optimized for. For most of that period the market gave it a “what if” valuation because the use case did not yet exist at scale.

Then AI happened. Hyperscalers needed gigawatts behind the meter, in 90 days, at 800 volt DC, with no combustion, no water cooling, no community pushback, and no waiting on the grid. That spec sheet did not exist as a customer requirement five years ago. Today it is the dominant procurement criterion for the largest infrastructure buildout in technology history.

Bloom did not pivot into AI power. They are AI power because the world finally caught up to the product they spent twenty-five years building. K.R.’s line tonight that “we will never be the bottleneck to our customers” is what twenty-five years of patient capital, deliberate manufacturing investment, and product refinement bought.

The Q&A Did the Real Work

Tonight’s prepared remarks were strong. The Q&A is where the call earned its place in the four-piece arc. K.R. answered analyst questions with operational disclosures that should reset how the bull case is modeled. Three of those disclosures all happened to land at “roughly an order of magnitude.” They compound. Most analysts will pick up one or two and miss the third. The bull case lives at the intersection of all three.

The first one, on capacity, is the cleanest. Listen to it directly:

K.R. Sridhar, Bloom Energy Q1 2026 earnings call. The 5 GW capacity disclosure that ends the Jefferies bear thesis.

That paragraph is the answer to Jefferies’ February Underperform/$92 PT, which was built explicitly on the concern that Bloom had not announced capacity expansion. Tonight K.R. disclosed the existing factory footprint can deliver 5 GW annually, 2.5x the previously stated ceiling. Bloom does not need to break ground on a new factory to convert the backlog. The capacity is sitting there.

That is one of three. The second is a manufacturing labor leverage equation that produces 200bps of gross margin expansion on top of an 80% revenue raise. The third is a deployment innovation K.R. himself flagged on the call as “a huge innovation we have not talked about” — and it changes customer concentration risk math.

Below the paywall: the second and third 10x’s that make the operating leverage equation work, the inference TAM expansion that resets the long-term model, the bear cases K.R. killed in two sentences, the customer concentration math after tonight, and updated targets.

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I spent the week on the floor at Mandalay Bay. The Wednesday headline was two new TPUs (8t for training, 8i for inference) and the commentary has spent the rest of the week debating specs. None of it was the actual story.

The actual story is the third announcement most people missed. NVIDIA simultaneously disclosed Vera Rubin A5X instances on Google Cloud scaling to 80,000 Rubin GPUs single-site and up to 960,000 multisite. Both silicon fleets ride Google’s new Virgo networking. Both are sold through the Gemini Enterprise Agent Platform. Google is not trying to beat NVIDIA. Google is making Google Cloud the neutral venue where TPU and NVIDIA both monetize enterprise agents.

That is the post. Everything that follows serves it.

The industry framing has been compute-driven. More parameters, more FLOPs, bigger clusters. That framing is out of date. Software is driving hardware. The workload shape, long-horizon enterprise agents running on any frontier model at production scale, is what forced the hardware decisions on both sides. The chip did not invent the workload. The workload invented the chip.

Worth saying out loud: it was a busy week beyond Cloud Next. OpenAI shipped GPT-5.5 mid-conference. DeepSeek shipped V4. The frontier model race kept compounding while Google was framing its silicon launch. None of these announcements happen in isolation. Every silicon decision Google made gets pressure-tested against the model that drops next week, and the pace right now is unforgiving.

Why I Went

I went to Cloud Next to gauge the energy on the floor and see which companies actually had commercial traction in the agentic era. Slide decks tell you what hyperscalers want to project. Booth traffic, customer conversations, and partner-pavilion energy tell you what is real. Four observations stood out before the silicon analysis even started.

The Anthropic booth had real energy. Consistent traffic across all three days, enterprise buyers and solution architects working through integration questions. Anthropic is the lighthouse customer for Google’s dual-fleet architecture, and the floor confirmed it. Anthropic quietly became one of the most important brands at the show.

The major SaaS providers were all there, and they were not retreating. ServiceNow, Salesforce, SAP, Workday, and the rest of the enterprise SaaS roster showed up as the orchestration and workflow layer for agents. The “AI eats software” bear case assumes agents replace SaaS. The floor said the opposite: SaaS providers are tools in the agentic world, not victims of it. This is the same thesis I laid out in The Orchestration Layer, and the Cloud Next floor was a strong real-time confirmation. Agents need workflow, identity, and orchestration plumbing. SaaS providers own that plumbing.

Enterprise AI deployment is earlier than the tape suggests. I spoke with IT managers from large healthcare and MRO (maintenance, repair, and overhaul) firms who have not yet started enterprise-wide AI projects. Not “haven’t gotten to production” — have not started. This cuts in two directions. The bull read: enterprise runway is enormous, hyperscaler capex is funding capacity that is years ahead of where adoption sits today, and we are still very early. The bear read: enterprise adoption is slower than the capex curve implies, and eventually that gap matters. I am in the bull camp on this, since Anthropic and OpenAI are filling the near-term capacity gap while the Fortune 500 catches up, but anyone modeling AI infrastructure should mark it.

The TPU-versus-NVIDIA business model is fundamentally different, and most market commentary misses it. NVIDIA sells you GPUs. NVIDIA gives you reference designs. NVIDIA partners with Supermicro, Dell, HPE, Foxconn, Quanta, and others to let you build your own racks and your own data centers. NVIDIA’s commercial logic is volume and ecosystem reach. Google does not sell you a TPU. Google does not give you a reference design. Google does not let you build a TPU rack in your own data center. Google’s commercial logic is rental: get you onto Google Cloud, then layer Vertex, BigQuery, Workspace, and the rest of the Google product stack on top. NVIDIA is a silicon company. Google is a cloud company that builds silicon as a tenant-attraction strategy. These are not the same business and they should not be modeled the same way. Salvator framed NVIDIA’s side of this directly when we spoke at the booth: NVIDIA has prioritized fungibility since the inception of deep learning, balancing AI training and inference performance with traditional ML, data analytics, visual computing, and scientific simulation. Custom silicon optimized narrowly for one workload sacrifices that breadth, which is part of why merchant silicon keeps winning at infrastructure managers who need to be ready for whatever workload comes next.

DeepMind was barely at Cloud Next, and that is informative. Gemini was everywhere — keynotes, demos, the agent platform, the Workspace integrations. DeepMind gave one talk. No booth, no meaningful floor presence. This is worth thinking about. Internally, Google appears to have separated the research lab (DeepMind) from the commercial product (Gemini). That structure is faster for execution, since the product team can ship without research-org gravity slowing it down, and it is the same separation Google ran historically between Google Research and Search. But it is also different from how OpenAI operates, where research and product sit in one building and ChatGPT iterates at lab speed. The implication is mixed. On the bull side, Google is treating Gemini as a real product franchise rather than a research demo, which is necessary for enterprise credibility. On the bear side, if the research-to-product handoff at Google ever weakens, the Anthropic dependency I described earlier becomes even more important, because Google needs another frontier-grade lab feeding workloads onto TPU regardless of what DeepMind ships next. This is one to watch.

The Anthropic fine print at Cloud Next. When Anthropic’s representative presented at the conference, the first slide carried fine print stating that Amazon Web Services is Anthropic’s primary cloud provider and primary training partner. Read that again. At Google Cloud Next, in front of Google’s enterprise customers, Anthropic disclaimed primary-provider status to Google in slide-one fine print. That language is presumably contractually required by the AWS agreement. It is also a real signal about the structural shape of the Google-Anthropic relationship. Anthropic is not a Google partner with AWS as a backup. Anthropic is an AWS partner that runs significantly on Google. The TPU commitment is enormous and real, but Google is the second cloud, not the first. This sharpens the Bear Two case I make later in the piece. Camp Two’s demand underwriter has a contractual primary somewhere else.

The Third Announcement

Two Google posts got the attention. A third disclosure, from NVIDIA, was the most commercially significant of the week. Ian Buck’s post titled “NVIDIA and Google Cloud Collaborate to Advance Agentic and Physical AI” laid out the dual-fleet architecture in detail.

Vera Rubin A5X on Google Cloud. Bare-metal Rubin NVL72 rack-scale systems, scaling to 80,000 Rubin GPUs single-site and up to 960,000 multisite. NVIDIA cites up to 10x lower inference cost per token and 10x higher token throughput per megawatt versus the prior generation. First-class NVIDIA deployment on a hyperscaler rival’s cloud, co-engineered between the two companies.

Rubin runs on Virgo. A5X uses NVIDIA ConnectX-9 SuperNICs combined with Google’s Virgo networking. Virgo is no longer TPU-only infrastructure. Google is turning it into the shared scale-out fabric for both TPU and NVIDIA fleets.

Gemini on Blackwell. Gemini runs in preview on Google Distributed Cloud on NVIDIA Blackwell and Blackwell Ultra. For some sovereign and confidential deployments, Google is positioning Gemini on NVIDIA Blackwell rather than making Gemini TPU-exclusive at the workload level.

Nemotron on Gemini Enterprise Agent Platform. NVIDIA’s open reasoning and multimodal models distributed through Google’s agent platform with a managed RL API built on NVIDIA NeMo RL. CrowdStrike is already fine-tuning Nemotron for cybersecurity on Managed Training Clusters with Blackwell GPUs.

OpenAI on Google Cloud. OpenAI is running large-scale inference for ChatGPT on NVIDIA GB300 (A4X Max VMs) and GB200 NVL72 (A4X VMs) on Google Cloud. Not Azure. Google Cloud, on NVIDIA silicon. Thinking Machines is doing the same on GB300 NVL72 for their Tinker API.

The Axes Forming Behind The Camps

Step back from the silicon layer and a clearer competitive structure emerges. Two axes are forming at the model-plus-infrastructure level, and each axis is more structurally integrated than the individual companies inside it suggest.

Axis One: Microsoft plus OpenAI plus NVIDIA. Azure Cloud, ChatGPT, CUDA stack. The model lab and the silicon vendor have converged on the same cloud for the workload most people associate with frontier AI. Azure remains the center of gravity, but OpenAI’s Google Cloud footprint proves even the strongest axis is diversifying.

Axis Two: Google plus Anthropic plus TPU. Google Cloud, Claude, TPU stack. Google’s reported $30 billion Anthropic TPU commitment is the anchor. And Google has strong incentive to deepen that relationship (reported additional capital into Anthropic, preferential TPU pricing, engineering co-investment) because Anthropic is the demand underwriter that makes the TPU fleet economically viable.

Google’s investment in Anthropic and NVIDIA’s earlier investment in OpenAI are directionally similar trades, even if the dollar scale differs. Both are proxy hedges on platform dominance: each silicon vendor is helping fund the model lab that anchors workload demand on its preferred stack. As Jensen acknowledged on the last earnings call, and as I wrote in The Chip Is Dead, Long Live The Factory, the bulk of TPU growth came from one customer. That customer is Anthropic. Today’s Cloud Next disclosures only deepened that dependency.

Here is the logic. NVIDIA has effectively locked up the leading-edge silicon supply chain. Google cannot outbid that supply chain and does not try to. Instead, Google wants to fill as much of its cloud capacity with NVIDIA GPUs as NVIDIA will sell it, because that is the silicon many customers already want to rent. The TPU fleet then becomes the optimized stack for Gemini-native workloads and Anthropic-scale demand. Supply timing matters too: TPU 8i ramp will take into next year, which is part of why Google leaned heavily on Rubin commitments now. The Vera Rubin order is doing double duty, capturing customers who want NVIDIA today and bridging Google’s own capacity until TPU 8i is at production volume.

If Anthropic’s TPU commitment scales, Camp Two survives as a real commercial counter-axis to Microsoft plus OpenAI. If Anthropic diversifies back toward NVIDIA or if Anthropic’s enterprise growth slows, the TPU fleet loses its demand underwriter and the economics get much harder. That is the single most important dependency in Google’s entire AI strategy, and it is the reason Google has every incentive to keep investing in Anthropic and keep pushing Claude workload onto TPU.

This is defense, not aggression. Google is not trying to beat NVIDIA at silicon. Google is trying to not-lose the frontier AI cloud battle to the Microsoft plus OpenAI axis, and the way it accomplishes that is by pairing Gemini with Claude on a shared TPU fleet while selling NVIDIA capacity alongside to capture the rest of the market. Two axes forming in parallel, each with its own model-plus-silicon pairing, each competing for enterprise agent workloads.

Below the paywall: the four conditions that gate Camp Two and why only Google clears them today, the bandwidth mechanism behind the 4x per-accelerator jump, the optical and memory supply-chain read-throughs, what the dual-fleet thesis means for NVDA and GOOGL, the three bear cases ranked by what I am actually watching, and the four signals from three days on the floor including the on-the-record Salvator conversation.

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The Story Everyone Knows Is Already Over

A lot of people have DM’d me since I posted my thread on the Dwarkesh Patel interview with Jensen Huang on Wednesday. I’m heading to Google Cloud Next this week, and paid subscribers will get my field notes from Vegas. But first, the framework.

For fifty years, progress in computing had a simple shape. Engineers shrank the transistors. Chips got faster. You bought the new one. That was the deal. Moore’s Law was the name people gave to the rhythm, and the rhythm was reliable enough that entire industries planned their roadmaps around it.

That story is over. Transistors have hit the atomic wall. At the leading edge of semiconductor manufacturing, the smallest features on a chip are now roughly ten atoms across. You cannot build a switch smaller than an atom. The physics that powered the digital revolution for half a century has quietly run out of room.

And yet the chips powering artificial intelligence keep getting dramatically faster, generation after generation, at a pace Moore’s Law never delivered even in its best years. NVIDIA’s newest platforms deliver roughly ten times the usable output of the generation they replace. Same factory. Same electrical grid. Same engineers. How?

The answer is that the thing being built is no longer a chip. It’s a factory. And the factory doesn’t just ship once. It keeps getting better after it ships.

From Chip to System to Factory

When Jensen Huang started calling NVIDIA’s approach extreme co-design, most of the industry treated it as marketing. It wasn’t. It was a description of what happens when every part of a computing system, including the chip, the memory, the networking between chips, the networking between racks, the cooling, the power delivery, and the software that schedules every operation, is designed together from day one rather than assembled from parts bought on the open market.

Consider what actually ships when NVIDIA delivers its latest platform. You don’t get a GPU. You get a rack. The rack contains 72 GPUs wired together so tightly that software treats them as one giant processor. Inside that rack is enough copper cable to stretch the length of two city blocks. The power density is the equivalent of two hundred suburban homes running full tilt inside a single seven-foot-tall cabinet. The cooling system circulates water warm enough to shower in, because the chips produce so much heat that traditional air cooling cannot keep up. Every one of those design decisions, from the cable routing to the water temperature to the way the GPUs share memory, was made so that the other decisions would work.

Now zoom out one level. That rack is itself just a unit inside a larger structure. At NVIDIA’s most recent GTC conference, the company unveiled five different rack types that work together: one for training, one for the fast answers a chatbot gives you, one for the memory that keeps long conversations coherent, one for the networking that ties everything together, one for the agents that do work on your behalf. None of these racks function alone. They function as a single building that converts electricity into intelligence. The industry has a name for this building now. It’s called an AI factory.

This is the first shift to understand. The product you are buying, if you are a hyperscaler or a government or a large enterprise, is not silicon. It is a factory that manufactures tokens, the small units of output that make up every answer ChatGPT gives, every image Midjourney renders, every line of code an AI coding assistant writes. The factory has a throughput measured in tokens per second. It has an input measured in megawatts of electricity. And like any factory, what matters is how much product it ships for each unit of electricity it consumes.

In six months, on the same silicon, one rack just got 2.7 times more productive. The Financial Times just reported that Anthropic cannot ship its most advanced model because the factories to run it do not exist yet. And Jensen Huang told Dwarkesh Patel the single line that explains three years of NVIDIA strategy, the line most viewers glossed over. Here is what it all means.

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Four companies. Four meetings. Four industries that look nothing alike on paper. And the same architecture underneath every pitch.

I spent two days this week listening to Ayar Labs CEO Mark Wade, Tenstorrent’s COO, Databricks CFO David Conte, and Wonder CEO Marc Lore walk through their businesses. Silicon photonics. RISC-V compute. Enterprise data. Food delivery. If you handed me the notes with the names stripped, I could not have told you which industry I was reading. Every one of them described the same moat: decouple the workload from the substrate, then own the substrate.

That is the reframe. Four layers, one moat. My bet coming out of those meetings is that this is the defining pattern of the next decade of infrastructure investing, and that most sell-side analysts are still siloed one layer at a time while the best operators are building horizontally.

A note on why I am writing about four private companies in a publication that is mostly about public-market allocation. The reason to track private companies at this stage is that they give you the framework to value the public companies they are competing with and working alongside. Ayar tells you something about Lumentum, Coherent, Credo, and Marvell. Tenstorrent tells you something about NVIDIA, AMD, and the HBM memory stack. Databricks tells you something about Oracle, Snowflake, and every enterprise SaaS incumbent. And Wonder, as I will argue below, tells you something about every publicly traded quick-service restaurant chain. What I heard from these four companies this week produced some of the most valuable public-market research I have collected all month.

Layer 1: Photons (Ayar Labs)

Ayar Labs is not new coverage for BEP. I have been tracking them since the Series C era, and most recently wrote about them in The Quiet Architect the week their $500 million Series E closed at a $3.75 billion valuation, positioning them as a direct competitor to Marvell’s Celestial AI Photonic Fabric in the scale-up optical race. Mark Wade was the most substantive speaker I heard all week, and the gap between the consensus public narrative on co-packaged optics and the pace he described was the widest of the four companies.

Total funding now stands at $870 million. NVIDIA has participated in four separate rounds. AMD in two. Intel Capital multiple times. TSMC is a multi-time strategic investor. The Hsinchu office opened the week before the conference. Investors still treating silicon photonics as a research program are reading the wrong news source. The capital stack says supply chain.

The 2028 ramp numbers: roughly 10 million optical chips per year at full run rate, 20 optical chips per GPU on leading-edge accelerators, ASPs between $100 and $1,000 per chip. At the midpoint that is a multi-billion dollar TAM that did not exist two years ago, concentrated into a handful of vendors inside TSMC’s COUPE flow. Wade was explicit that the path runs through TSMC specifically: “You are building in that ecosystem or you are probably not very relevant for the next few years.” That is a foundry concentration argument with real consequences for anyone trying to enter the market outside the TSMC orbit.

The technical claim is the part most investors underweight. A current Blackwell GPU escapes with about 20 Tbps of aggregate bandwidth across electrical I/O. Ayar’s 2028 target is roughly 10x the bandwidth, 10x the radix, and a distance ceiling that goes from one meter of copper to a hundred meters of fiber. That is not a speed improvement. That is a topology change. The rack stops being the unit of deployment. Two years of TSMC yield improvement, laser reliability gains, and UCIe standardization closed the gap from “maybe” to “inevitable.”

The reliability inversion Wade described is the update that matters most. Reliability used to be the argument against co-packaged optics. Now it is the argument for co-packaged optics, because copper reliability is degrading faster than optical reliability is improving. I wrote in The Great Photonic Divergence that the optical transition was a when-not-if question. Wade told the room the “when” is back half of 2028. GPU customers are no longer asking whether photonics survives the compute fabric. They are asking how many millions of units per month his team can deliver.

Layer 2: Silicon (Tenstorrent)

Tenstorrent was the one company I sat with directly this week. “We are Linux to NVIDIA’s Windows.” That was the pitch. Open compilers on GitHub. RISC-V instead of Arm. GDDR6 and on-chip SRAM instead of HBM. Ethernet mesh instead of NVLink. No CoWoS silicon interposer. No HBM supply queue. No CUDA lock-in. Jim Keller as CTO. Pricing that starts at $999 for a Blackhole PCIe card and $11,999 for an 80-billion-parameter workstation.

The architecture is the thesis. In The Packaging Paradox I argued CoWoS plus HBM is the real AI bottleneck, not transistor density. Tenstorrent routes around both by keeping weights in on-chip SRAM, leaning on commodity GDDR6, and skipping the HBM allocation fight entirely. The trade is weaker training throughput versus B200 class, but inference on LLMs and video generation is where they point the marketing. The benchmark claims out of the meeting were aggressive: “5 to 15x” speed advantages over NVIDIA B200, Groq, and SambaNova on targeted inference workloads. Vendor-published numbers. I treat them as positioning until third parties confirm at the May 1 TT Deploy event in San Francisco.

The real question for investors is whether Tenstorrent has a defensible place against NVIDIA, or whether it ends up as another SambaNova or Cerebras: real technology, real capital, no durable dent in NVIDIA’s share. In NVIDIA’s Inference Stack Depth Strategy I argued that “they sell chips; NVIDIA sells stack depth.” NVIDIA’s moat is not the GPU. It is Mellanox plus NVLink plus CUDA plus Run:ai plus Dynamo plus the Groq IP license plus TSMC allocation priority plus the installed developer base. A competitor who wins on the chip alone does not win. Tenstorrent understands this, which is why they are not competing on the chip alone.

My verdict: Tenstorrent has a real place, but a bounded one. Three vectors matter.

First, sovereignty buyers. Tenstorrent’s COO described sovereign buyers, countries like Brazil, telling him exactly what I wrote in AI for the Rest of the World. Countries do not want to bet national AI infrastructure on a single US vendor that can be cut off by export policy. Tenstorrent already has announced sovereign partnerships with Cyprus, UAE, Japan, and Korea. RISC-V plus open compilers plus commodity GDDR6 is the sovereign-compliant alternative NVIDIA structurally cannot match without giving up CUDA margin. Bounded TAM, but real.

Second, latency-bound workloads. XTX Markets invested $200 million because shaving microseconds off inference in algorithmic trading is worth buying a second-source silicon stack. Similar logic applies to high-frequency anomaly detection, real-time fraud screening, and on-premise sensitive-data inference where sending workloads to cloud GPU is not an option. These are not markets NVIDIA loses. They are markets NVIDIA has structurally said no to.

Third, the HBM-sidestep bet. SanDisk is co-developing floating-gate flash for AI weights because weights do not change every ten nanoseconds, so paying HBM prices to store them is architecturally wasteful. If that product works at scale, inference TCO shifts meaningfully. Not enough to break CUDA, but enough to make a class of workloads cheaper on open hardware.

Floor case: profitable sovereign plus algorithmic-trading plus developer workstation revenue. Ceiling case: the May 1 benchmarks get independently validated and the Quasar 4nm chiplet generation ships on time. I am watching, not owning.

Layer 3: Data (Databricks)

Databricks reported a $5.4 billion revenue run rate growing more than 65% year-over-year in Q4 2025, with $1.4 billion from AI products alone. Net retention is above 140%. More than 800 customers spend above $1 million annually, more than 70 above $10 million. Free cash flow is positive. The Series L in December 2025 raised $4 billion at a $134 billion valuation, roughly 25x annualized revenue.

Three things landed from the CFO’s session. The Neon Postgres acquisition is not a database play, it is an agent play: agents generate orders of magnitude more queries than humans, and running those on legacy enterprise database pricing does not pencil. Databricks has open-sourced every core technology where customers derive value and captures revenue at the layer above. On security and SIEM, the entry criteria are “adjacent to what we do” and “unfair advantage.” If you index your enterprise inside Databricks to train models against, you may as well run anomaly detection on the same substrate.

I wrote in Is Software Dead? that “Systems of record dominate digital context today, your CRM knows your customers, your ERP knows your inventory, your HRIS knows your employees.” Databricks is doing the same thing Oracle is doing from a different direction. Oracle owns the relational substrate and is adding agentic AI on top. Databricks owns the lakehouse and is adding a transactional database, agents, and security underneath. Both converge on the layer where private enterprise data meets foundation models. Whoever owns that layer collects rent on every inference call an enterprise ever makes against its own data.

The fourth company is the one most readers will miss. It is also the one with the clearest public-market read-through, and the reason holders of legacy QSR and fast-casual equity should calendar the S-1.

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